Reduction of Current Mismatch in PLL Charge Pump. - H. Md. Shuaeb Fazeel; Leneesh Raghavan; Chandrasekaran Srinivasaraman; Manish Jain (ISVLSI, 2009)

A 4.1pJ/b 16Gb/s coded differential bidirectional parallel electrical link. - Amir Amirkhany; Kambiz Kaviani; Ali-Azam Abbasfar; H. Md. Shuaeb Fazeel; Wendemagegnehu T. Beyene; Chikara Hoshino; Chris J. Madden; Ken Chang; Chuck Yuan (ISSCC, 2012)

A 4.1-pJ/b, 16-Gb/s Coded Differential Bidirectional Parallel Electrical Link. - Amir Amirkhany; Kambiz Kaviani; Ali-Azam Abbasfar; H. Md. Shuaeb Fazeel; Wendemagegnehu T. Beyene; Chikara Hoshino; Chris J. Madden; Ken Chang; Chuck Yuan (IEEE J. Solid State Circuits, 2012)

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface. - Amir Amirkhany; Jason Wei; Navin K. Mishra; Jie Shen 010; Wendemagegnehu T. Beyene; Catherine Chen 005; T. J. Chin; Deborah Dressler; Charlie Huang; Vijay P. Gadde; Mohammad Hekmat; Kambiz Kaviani; et al. (IEEE J. Solid State Circuits, 2012)

A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface. - Kambiz Kaviani; Ting Wu 003; Jason Wei; Amir Amirkhany; Jie Shen 010; T. J. Chin; Chintan Thakkar; Wendemagegnehu T. Beyene; Norman Chan; Catherine Chen 005; Bing Ren Chuang; Deborah Dressler; et al. (IEEE J. Solid State Circuits, 2012)