A block-parallel signal processing system for CMOS image sensor with three-dimensional structure. - Kouji Kiyoyama; Kang Wook Lee 002; Takafumi Fukushima; H. Naganuma; Hiroaki Kobayashi; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2010)

A very low area ADC for 3-D stacked CMOS image processing system. - Kouji Kiyoyama; Kang Wook Lee 002; Takafumi Fukushima; H. Naganuma; H. Kobayashi; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2011)

A 37 × 37 pixels artificial retina chip with edge enhancement function for 3-D stacked fully implantable retinal prosthesis. - H. Naganuma; Kouji Kiyoyama; Tetsu Tanaka (BioCAS, 2012)

Impact of 3-D integration process on memory retention characteristics in thinned DRAM chip for 3-D memory. - Kang Wook Lee 002; Seiya Tanikawa; Mariappan Murugesan; H. Naganuma; Jichoel Bea; Takafumi Fukushima; Tetsu Tanaka; Mitsumasa Koyanagi (3DIC, 2013)

Low write power and Field-free sub-ns write speed SOT-MRAM cell with Design Technology of Canted SOT structure and Magnetic Anisotropy for NVM. - T. V. A. Nguyen; H. Naganuma; H. Honjo; Y. Sato; T. Tanigawa; S. Ikeda; T. Endoh (IMW, 2025)