Device engineering guidelines for performance boost in IGZO front gated TFTs based on defect control. - S. Subhechha; Nouredine Rassoul; Attilio Belmonte; Hubert Hody; Harold Dekkers; Michiel J. van Setten; Adrian Vaisman Chasin; Shamin H. Sharifi; K. Banerjee; H. Puliyalil; Shreya Kundu; M. Pak; et al. (ICICDT, 2022)

Ultra-low Leakage IGZO-TFTs with Raised Source/Drain for Vt > 0 V and Ion > 30 µA/µm. - S. Subhechha; Nouredine Rassoul; Attilio Belmonte; Hubert Hody; Harold Dekkers; Michiel J. van Setten; Adrian Vaisman Chasin; Shamin H. Sharifi; S. Sutar; L. Magnarin; Umberto Celano; H. Puliyalil; et al. (VLSI Technology and Circuits, 2022)

Lowest IOFF < 3×10-21 A/μm in capacitorless DRAM achieved by Reactive Ion Etch of IGZO-TFT. - Attilio Belmonte; Shreya Kundu; S. Subhechha; Adrian Vaisman Chasin; Nouredine Rassoul; Harold Dekkers; H. Puliyalil; F. Seidel; P. Carolan; Romain Delhougne; Gouri Sankar Kar (VLSI Technology and Circuits, 2023)

Accurate off-current evaluation by parasitic capacitance extraction in capacitor-less DRAM cells. - Daisuke Matsubayashi; Subhali Subhechha; Hyungrock Oh; Nouredine Rassoul; Shamin Houshmand Sharifi; Yiqun Wan; Shreya Kundu; Harinarayanan Puliyalil; Harold Dekkers; Alexandru Pavel; Inhee Lee 004; Gouri Sankar Kar; et al. (IMW, 2025)

Hole-Side Airgap Integration as Enabler for 3D NAND Flash Z-Pitch Scaling. - S. Rachidi; S. Ramesh; Devin Verreck; J. Loyo; Y. Jeong; H. Puliyalil; Jie Li; F. Seidel; Geert Van Den Bosch; Maarten Rosmeulen (IMW, 2025)