Optimized reversible BCD adder using new reversible logic gates - H. R. Bhagyalakshmi; M. K. Venkatesha (CoRR, 2010)

Design of Parity Preserving Logic Based Fault Tolerant Reversible Arithmetic Logic Unit. - Rakshith Saligram; Shrihari Shridhar Hegde; Shashidhar A. Kulkarni; H. R. Bhagyalakshmi; M. K. Venkatesha (CoRR, 2013)