Design & Development of High Speed LVDS Receiver with Cold-Spare Feature in SCL's 0.18 µm CMOS Process. - Munish Malik; Ajay Kumar; H. S. Jatana (VDAT, 2017)

A Physics-Based Variability-Aware Methodology to Estimate Critical Charge for Near-Threshold Voltage Latches. - Chaudhry Indra Kumar; Ishant Bhatia; Arvind Kumar Sharma; Deep Sehgal; H. S. Jatana; Anand Bulusu (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Total ionizing dose hardness analysis of transistors in commercial 180 nm CMOS technology. - Mukesh Kumar; Jagpal Singh Ubhi; Sanjeev Basra; Anuj Chawla; H. S. Jatana (Microelectron. J., 2021)