A 14-bit 80-kHz sigma-delta A/D converter: modeling, design and performance evaluation. - Steven R. Norsworthy; Irving G. Post; H. Scott Fetterman (IEEE J. Solid State Circuits, 1989)

A 10-b 20-Msample/s analog-to-digital converter. - Stephen H. Lewis; H. Scott Fetterman; George F. Gross; Ravi Ramachandran; T. R. Viswanathan 001 (IEEE J. Solid State Circuits, 1992)

A 250-mW, 8-b, 52-Msamples/s parallel-pipelined A/D converter with reduced number of amplifiers. - Krishnaswamy Nagaraj; H. Scott Fetterman; Joseph Anidjar; Stephen H. Lewis; Robert G. Renninger (IEEE J. Solid State Circuits, 1997)

CMOS pipelined ADC employing dither to improve linearity. - H. Scott Fetterman; David G. Martin; David A. Rich (CICC, 1999)