Parallel in Sequence - Towards the Architecture of an Elementary Cortical Processor. - Edgar Körner; T. Tsuda; H. Shimizu (Parallel Algorithms and Architectures, 1987)

Control of sensory processing - a hypothesis on and simulation of the architecture of an elementary cortical prosessor. - Edgar Körner; M. Gross; Andreas Richter; H. Shimizu (Parcella, 1988)

Knowledge Media Station. - Y. Hosono; H. Kumagai; H. Shimizu; M. Sumida; Akikazu Takeuchi; N. Takiguchi; T. Wake; T. Yamaoka (LP, 1989)

A single-chip 8-band CMOS transceiver for W-CDMA(HSPA) / GSM(GPRS) / EDGE with digital interface. - Hiroshi Yoshida; Takehiko Toyoda; T. Yasuda; Yosuke Ogasawara; M. Ishii; T. Murasaki; Gaku Takemura; Masaomi Iwanaga; T. Takida; Yuta Araki; T. Hashimoto; K. Sami; et al. (ESSCIRC, 2008)