Performance Optimization of Flagged BCD Adder. - Nidhi Chandak; H. V. Jayashree; Ghanshyam N. Patil; Nidhi C. Rao (ICETET, 2013)

Progress in Reversible Processor Design: A Novel Methodology for Reversible Carry Look-Ahead Adder. - Himanshu Thapliyal; H. V. Jayashree; A. N. Nagamani; Hamid R. Arabnia (Trans. Comput. Sci., 2013)

Design of Dedicated Reversible Quantum Circuitry for Square Computation. - H. V. Jayashree; Himanshu Thapliyal; Vinod Kumar Agrawal (VLSID, 2014)

Ancilla-input and garbage-output optimized design of a reversible quantum integer multiplier. - H. V. Jayashree; Himanshu Thapliyal; Hamid R. Arabnia; Vinod Kumar Agrawal (J. Supercomput., 2016)

Reversible circuit optimization using modified toffoli templates. - Mridula J. Deshpande; H. V. Jayashree; Vinod Kumar Agrawal (ICACCI, 2017)

Reversible circuit design for GCD computation in cryptography algorithms. - H. V. Jayashree; Skanda Kotethota; Vinod Kumar Agrawal (Int. J. Circuit Theory Appl., 2017)

Efficient Circuit Design of Reversible Square. - H. V. Jayashree; Himanshu Thapliyal; Vinod Kumar Agrawal (Trans. Comput. Sci., 2017)

Design Approaches for Resource and Performance Optimization of Reversible BCD Addition and Unified BCD Addition/Subtraction Circuits. - H. V. Jayashree; Sharan Patil; Vinod Kumar Agrawal (J. Circuits Syst. Comput., 2018)