22.1 A 0.275pJ/b 42Gb/s/pin Clock-Referenced PAM3 Transceiver Tolerant to Supply Noise, Reference Offset and Crosstalk for Chiplets and Short-Reach Memory Interfaces. - Kahyun Kim; Jung-Hun Park; Ha-Jung Park; Jia Park; Jihee Kim; Woo-Seok Choi (ISSCC, 2025)

A 4 × 32 Gb/s 1.8 pJ/bit Collaborative Baud-Rate CDR With Background Eye-Climbing Algorithm and Low-Power Global Clock Distribution. - Jihee Kim; Jia Park; Jiwon Shin; Hanseok Kim; Kahyun Kim; Haengbeom Shin; Ha-Jung Park; Woo-Seok Choi (IEEE J. Solid State Circuits, 2025)