Application of fast layout synthesis environment to dividers evaluation. - A. Houelle; Habib Mehrez; Nicolas Vaucher; Luis A. Montalvo; Alain Guyot (IEEE Symposium on Computer Arithmetic, 1995)

Comparison of the layout synthesis of radix-2 and pseudo-radix-4 dividers. - Alain Guyot; Luis A. Montalvo; A. Houelle; Habib Mehrez; Nicolas Vaucher (VLSI Design, 1995)

Teaching the design of a chip under the Cadence Opus environment using the Alliance cell libraries. - Mourad Aberbour; Anne Derieux; Habib Mehrez; Nicolas Vaucher (MSE, 1997)

On portable macrocell FPU generators for division and square root operators complying to the full IEEE-754 standard. - Mourad Aberbour; A. Houelle; Habib Mehrez; Nicolas Vaucher; Alain Guyot (IEEE Trans. Very Large Scale Integr. Syst., 1998)

A System-On-A-Chip for Pattern Recognition Architecture and Design Methodology. - Mourad Aberbour; Habib Mehrez; François Durbin; Jacques Haussy; P. Lalande; André Tissot (CAMP, 2000)

A family of redundant multipliers dedicated to fast computation for signal processing. - Yannick Dumonteix; Habib Mehrez (ISCAS, 2000)

Customizable DSP architecture for ASIP core design. - Yann Bajot; Habib Mehrez (ISCAS (4), 2001)

A fast and low-power distance computation unit dedicated to neural networks, based on redundant arithmetic. - Yannick Dumonteix; Yann Bajot; Habib Mehrez (ISCAS (4), 2001)

A floating-point unit using stochastic arithmetic compliant with the IEEE-754 standard. - Roselyne Chotin; Habib Mehrez (ICECS, 2002)

Cycle-accurate energy estimation in system level descriptions of embedded systems. - Ana Belén Abril García; Jean Gobert; Thomas Dombek; Habib Mehrez; Frédéric Pétrot (ICECS, 2002)

Hardware Implementation of Discrete Stochastic Arithmetic. - Roselyne Avot-Chotin; Habib Mehrez (Numer. Algorithms, 2004)

Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation. - Zied Marrakchi; Hayder Mrabet; Habib Mehrez (ReConFig, 2005)

Implementation of Scalable Embedded FPGA for SOC. - Hayder Mrabet; Zied Marrakchi; Habib Mehrez; André Tissot (ReCoSoC, 2005)

A multilevel hierarchical interconnection structure for FPGA. - Hayder Mrabet; Zied Marrakchi; Pierre Souillot; Habib Mehrez (FPGA, 2006)

Configuration tools for a new multilevel hierarchical FPGA. - Zied Marrakchi; Hayder Mrabet; Habib Mehrez (FPGA, 2006)

Performances improvement of FPGA using novel multilevel hierarchical interconnection structure. - Hayder Mrabet; Zied Marrakchi; Pierre Souillot; Habib Mehrez (ICCAD, 2006)

A new Multilevel Hierarchical MFPGA and its suitable configuration tools. - Zied Marrakchi; Hayder Mrabet; Habib Mehrez (ISVLSI, 2006)

Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure. - Hayder Mrabet; Zied Marrakchi; Pierre Souillot; Habib Mehrez; André Tissot (ReCoSoC, 2006)

Efficient Mesh of Tree Interconnect for FPGA Architecture. - Zied Marrakchi; Hayder Mrabet; Christian Masson; Habib Mehrez (FPT, 2007)

Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances. - Zied Marrakchi; Hayder Mrabet; Christian Masson; Habib Mehrez (NOCS, 2007)

A new coarse-grained FPGA architecture exploration environment. - Husain Parvez; Zied Marrakchi; Umer Farooq 001; Habib Mehrez (FPT, 2008)

Efficient tree topology for FPGA interconnect network. - Zied Marrakchi; Hayder Mrabet; Emna Amouri; Habib Mehrez (ACM Great Lakes Symposium on VLSI, 2008)

Arithmetic Data Path Optimization Using Borrow-Save Representation. - Sophie Belloeil; Roselyne Chotin-Avot; Habib Mehrez (ISVLSI, 2008)

The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture. - Umer Farooq 001; Zied Marrakchi; Hayder Mrabet; Habib Mehrez (ReConFig, 2008)

Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-Grained FPGAs. - Husain Parvez; Zied Marrakchi; Habib Mehrez (ReConFig, 2008)

Estimation et optimisation de la consommation dans les SoC utilisant la simulation précise au cycle. - Ana Abril; Habib Mehrez; Frédéric Pétrot; Jean Gobert; Carolina Miro (Tech. Sci. Informatiques, 2008)

ASIF: Application Specific Inflexible FPGA. - Husain Parvez; Zied Marrakchi; Habib Mehrez (FPT, 2009)

Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA. - Emna Amouri; Hayder Mrabet; Zied Marrakchi; Habib Mehrez (ICECS, 2009)

Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing. - Emna Amouri; Hayder Mrabet; Zied Marrakchi; Habib Mehrez (ReConFig, 2009)

FPGA Interconnect Topologies Exploration. - Zied Marrakchi; Hayder Mrabet; Umer Farooq 001; Habib Mehrez (Int. J. Reconfigurable Comput., 2009)

Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGA. - Emna Amouri; Zied Marrakchi; Habib Mehrez (APCCAS, 2010)

On the optimization of FPGA area depending on target applications. - Zied Marrakchi; Husain Parvez; Alp Kiliç; Habib Mehrez; Hmaied Marrakchi (APCCAS, 2010)

Application Specific FPGA Using Heterogeneous Logic Blocks. - Husain Parvez; Zied Marrakchi; Habib Mehrez (ARC, 2010)

Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only). - Husain Parvez; Zied Marrakchi; Habib Mehrez (FPGA, 2010)

A flexible realtime system for broadband time-frequency analysis in 130 NM CMOS. - Ludovic Noury; Habib Mehrez (ICECS, 2010)

Routability driven placement for mesh-based FPGA architecture. - Mariem Turki; Mohamed Abid; Zied Marrakchi; Habib Mehrez (IDT, 2010)

Comparison between Heterogeneous Mesh-Based and Tree-Based Application Specific FPGA. - Umer Farooq 001; Husain Parvez; Zied Marrakchi; Habib Mehrez (ARC, 2011)

Stratus: Free design of highly parametrized VLSI modules interoperable with commercial tools. - Sophie Belloeil-Dupuis; Roselyne Chotin-Avot; Habib Mehrez (ISQED, 2011)

Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA. - Emna Amouri; Zied Marrakchi; Habib Mehrez (ReCoSoC, 2011)

Exploration of Heterogeneous FPGA Architectures. - Umer Farooq 001; Husain Parvez; Habib Mehrez; Zied Marrakchi (Int. J. Reconfigurable Comput., 2011)

Application-Specific FPGA using heterogeneous logic blocks. - Husain Parvez; Zied Marrakchi; Alp Kiliç; Habib Mehrez (ACM Trans. Reconfigurable Technol. Syst., 2011)

A logic sharing synthesis tool for mutually exclusive applications. - Alp Kiliç; Zied Marrakchi; Matthieu Tuna; Habib Mehrez (DTIS, 2012)

Efficient parallel-pipelined GHASH for message authentication. - Karim M. Abdellatif; Roselyne Chotin-Avot; Habib Mehrez (ReConFig, 2012)

Multi-FPGA prototyping environment: Large benchmark generation and signals routing. - Mariem Turki; Habib Mehrez; Zied Marrakchi (ReConFig, 2012)

Design for prototyping of a parameterizable cluster-based Multi-Core System-on-Chip on a multi-FPGA board. - Qingshan Tang; Habib Mehrez; Matthieu Tuna (RSP, 2012)

A new heterogeneous tree-based application specific FPGA and its comparison with mesh-based application specific FPGA. - Umer Farooq 001; Husain Parvez; Habib Mehrez; Zied Marrakchi (Microprocess. Microsystems, 2012)

Designing a 3D tree-based FPGA: Optimization of butterfly programmable interconnect topology using 3D technology. - Vinod Pangracious; Habib Mehrez; Zied Marrakchi (3DIC, 2013)

Data level parallelism for H264/AVC baseline intra-prediction chain on MPSoC. - Nidhameddine Belhadj; Nejmeddine Bahri; Mohamed Ali Ben Ayed; Zied Marrakchi; Habib Mehrez (SSD, 2013)

Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA. - Vinod Pangracious; Zied Marrakchi; Emna Amouri; Habib Mehrez (ARC, 2013)

Automatic Design Flow for Creating a Custom Multi-FPGA Board Netlist. - Qingshan Tang; Matthieu Tuna; Zied Marrakchi; Habib Mehrez (ARC, 2013)

Iterative Routing Algorithm of Inter-FPGA Signals for Multi-FPGA Prototyping Platform. - Mariem Turki; Zied Marrakchi; Habib Mehrez; Mohamed Abid (ARC, 2013)

Architecture level TSV count minimization methodology for 3D tree-based FPGA. - Vinod Pangracious; Habib Mehrez; Zied Marrakchi (COOL Chips, 2013)

High performance 3-dimensional heterogeneous tree-based FPGA architectures (HT-FPGA). - Vinod Pangracious; Habib Mehrez; Umer Farooq 001; Zied Marrakchi (FPGAworld, 2013)

A defect-tolerant cluster in a mesh SRAM-based FPGA. - Arwa Ben Dhia; Saif-Ur Rehman; Adrien Blanchardon; Lirida A. B. Naviner; Mounir Benabdenbi; Roselyne Chotin-Avot; Emna Amouri; Habib Mehrez; Zied Marrakchi (FPT, 2013)

Design and optimization of heterogeneous tree-based FPGA using 3D technology. - Vinod Pangracious; Zied Marrakchi; Habib Mehrez (FPT, 2013)

Physical design exploration of 3D tree-based FPGA architecture. - Vinod Pangracious; Emna Amouri; Habib Mehrez; Zied Marrakchi (ACM Great Lakes Symposium on VLSI, 2013)

TSV count minimization and thermal analysis for 3D Tree-based FPGA. - Vinod Pangracious; Habib Mehrez; Zied Marrakchi (ICICDT, 2013)

Partitioning constraints and signal routing approach for multi-FPGA prototyping platform. - Mariem Turki; Habib Mehrez; Zied Marrakchi; Mohamed Abid (ISSoC, 2013)

Efficient AES-GCM for VPNs using FPGAs. - Karim M. Abdellatif; Roselyne Chotin-Avot; Habib Mehrez (MWSCAS, 2013)

Efficient state-dependent power model for multi-bit flip-flop banks. - Jung Kyu Chae; Severine Bertrand; Pierre-Francois Ollagnon; Paul Mougeat; Jean-Arnaud Francois; Roselyne Chotin-Avot; Habib Mehrez (MWSCAS, 2013)

Protecting FPGA bitstreams using authenticated encryption. - Karim M. Abdellatif; Roselyne Chotin-Avot; Habib Mehrez (NEWCAS, 2013)

Designing 3D tree-based FPGA: Interconnect optimization and thermal analysis. - Vinod Pangracious; Habib Mehrez; Zied Marrakchi (NEWCAS, 2013)

Lightweight and compact solutions for secure reconfiguration of FPGAs. - Karim M. Abdellatif; Roselyne Chotin-Avot; Habib Mehrez (ReConFig, 2013)

Improved method for parallel AES-GCM cores using FPGAs. - Karim M. Abdellatif; Roselyne Chotin-Avot; Habib Mehrez (ReConFig, 2013)

Efficient multilevel interconnect topology for cluster-based mesh FPGA architecture. - Emna Amouri; Adrien Blanchardon; Roselyne Chotin-Avot; Habib Mehrez; Zied Marrakchi (ReConFig, 2013)

Exploration environment for 3D heterogeneous tree-based FPGA architectures (3D HT-FPGA). - Vinod Pangracious; Habib Mehrez; Nizar Beltaief; Zied Marrakchi; Umer Farooq 001 (ReConFig, 2013)

Routing algorithm for multi-FPGA based systems using multi-point physical tracks. - Qingshan Tang; Matthieu Tuna; Habib Mehrez (RSP, 2013)

A formalism of the specifications for library development. - Jung Kyu Chae; Paul Mougeat; Jean-Arnaud Francois; Roselyne Chotin-Avot; Habib Mehrez (SoCC, 2013)

High speed authenticated encryption for slow changing key applications using reconfigurable devices. - Karim M. Abdellatif; Roselyne Chotin-Avot; Habib Mehrez (Wireless Days, 2013)

Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA. - Emna Amouri; Habib Mehrez; Zied Marrakchi (Int. J. Reconfigurable Comput., 2013)

Frequency Optimization Objective during System Prototyping on Multi-FPGA Platform. - Mariem Turki; Zied Marrakchi; Habib Mehrez; Mohamed Abid (Int. J. Reconfigurable Comput., 2013)

Exploring redundant arithmetics in computer-aided design of arithmetic datapaths. - Sophie Belloeil-Dupuis; Roselyne Chotin-Avot; Habib Mehrez (Integr., 2013)

Exploration and optimization of a homogeneous tree-based application specific inflexible FPGA. - Umer Farooq 001; Husain Parvez; Habib Mehrez; Zied Marrakchi (Microelectron. J., 2013)

A defect-tolerant area-efficient multiplexer for basic blocks in SRAM-based FPGAs. - Arwa Ben Dhia; Samuel N. Pagliarini; Lirida Alves de Barros Naviner; Habib Mehrez; Philippe Matherat (Microelectron. Reliab., 2013)

Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation. - Sonda Chtourou; Mohamed Abid; Vinod Pangracious; Emna Amouri; Zied Marrakchi; Habib Mehrez (3DIC, 2014)

FPGA-Based High Performance AES-GCM Using Efficient Karatsuba Ofman Algorithm. - Karim M. Abdellatif; Roselyne Chotin-Avot; Habib Mehrez (ARC, 2014)

MPSoC architecture for Component Level Parallelism of H.264/AVC intra prediction encoding chain on SoCLib platform. - Nidhameddine Belhadj; Mohamed Ali Ben Ayed; Nouri Masmoudi; Zied Marrakchi; Habib Mehrez (ATSIP, 2014)

Power consumption analysis for mesh based FPGA. - Sonda Chtourou; Mohamed Abid; Zied Marrakchi; Habib Mehrez (DTIS, 2014)

Exploration and optimization of heterogeneous interconnect fabric of 3D tree-based FPGA. - Vinod Pangracious; Zied Marrakchi; Nizar Beltaief; Habib Mehrez; Umer Farooq 001 (DTIS, 2014)

Performance Comparison between Multi-FPGA Prototyping Platforms: Hardwired Off-the-Shelf, Cabling, and Custom. - Qingshan Tang; Matthieu Tuna; Habib Mehrez (FCCM, 2014)

Towards high performance GHASH for pipelined AES-GCM using FPGAs (abstract only). - Karim M. Abdellatif; Roselyne Chotin-Avot; Zied Marrakchi; Habib Mehrez; Qingshan Tang (FPGA, 2014)

Future inter-FPGA communication architecture for multi-FPGA based prototyping (abstract only). - Qingshan Tang; Matthieu Tuna; Habib Mehrez (FPGA, 2014)

Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security. - Emna Amouri; Shivam Bhasin; Yves Mathieu; Tarik Graba; Jean-Luc Danger; Habib Mehrez (FPL, 2014)

Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy. - Adrien Blanchardon; Roselyne Chotin-Avot; Habib Mehrez; Emna Amouri (FPL, 2014)

Low-power comb decimation filter for RF Sigma-Delta ADCs. - Alp Kiliç; Delaram Haghighitalab; Habib Mehrez; Hassan Aboushady (ISCAS, 2014)

Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA. - Saif-Ur Rehman; Adrien Blanchardon; Arwa Ben Dhia; Mounir Benabdenbi; Roselyne Chotin-Avot; Lirida A. B. Naviner; Lorena Anghel; Habib Mehrez; Emna Amouri; Zied Marrakchi (ISVLSI, 2014)

A reference-based specification tool for creating reliable library development specifications. - Jung Kyu Chae; Paul Mougeat; Jean-Arnaud Francois; Roselyne Chotin-Avot; Habib Mehrez (NEWCAS, 2014)

Impact of defect tolerance techniques on the criticality of a SRAM-based mesh of cluster FPGA. - Adrien Blanchardon; Roselyne Chotin-Avot; Habib Mehrez; Emna Amouri (ReConFig, 2014)

Multi-FPGA prototyping board issue: the FPGA I/O bottleneck. - Qingshan Tang; Habib Mehrez; Matthieu Tuna (ICSAMOS, 2014)

Flexible reconfigurable architecture for DSP applications. - Abdulfattah Mohammad Obeid; Syed Manzoor Qasim; Mohammed S. BenSaleh; Zied Marrakchi; Habib Mehrez; Heni Ghariani; Mohamed Abid (SoCC, 2014)

On wiring delays reduction of tree-based FPGA using 3-D fabric. - Vinod Pangracious; Mohamed Sahbi Marrakchi; Habib Mehrez; Zied Marrakchi (SoCC, 2014)

MPSoC Architecture for Macro Blocks Line Partitioning of H.264/AVC Encoder. - Nidhameddine Belhadj; Zied Marrakchi; Mohamed Ali Ben Ayed; Nouri Masmoudi; Habib Mehrez (Int. J. Embed. Real Time Commun. Syst., 2014)

Low cost solutions for secure remote reconfiguration of FPGAs. - Karim M. Abdellatif; Roselyne Chotin-Avot; Habib Mehrez (Int. J. Embed. Syst., 2014)

A Top-Down Optimization Methodology for Mutually Exclusive Applications. - Alp Kiliç; Zied Marrakchi; Habib Mehrez (Int. J. Reconfigurable Comput., 2014)

Authenticated encryption on FPGAs from the static part to the reconfigurable part. - Karim M. Abdellatif; Roselyne Chotin-Avot; Habib Mehrez (Microprocess. Microsystems, 2014)

Architecture level optimization of 3-dimensional tree-based FPGA. - Vinod Pangracious; Emna Amouri; Zied Marrakchi; Habib Mehrez (Microelectron. J., 2014)

Power grid redundant path contribution in system on chip (SoC) robustness against electromigration. - Boukary Ouattara; Lise Doyen; David Ney; Habib Mehrez; Pirouz Bazargan-Sabet (Microelectron. Reliab., 2014)

Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization. - Sonda Chtourou; Zied Marrakchi; Vinod Pangracious; Emna Amouri; Habib Mehrez; Mohamed Abid (ARC, 2015)

Signal multiplexing approach to improve inter-FPGA bandwidth of prototyping platform. - Mariem Turki; Zied Marrakchi; Habib Mehrez; Mohamed Abid (Des. Autom. Embed. Syst., 2015)

H.264/AVC high definition intra coding implementation on multiprocessor system on chip technology architecture. - Nidhameddine Belhadj; Nejmeddine Bahri; Zied Marrakchi; Mohamed Ali Ben Ayed; Nouri Masmoudi; Habib Mehrez (IET Comput. Digit. Tech., 2015)

Design and Optimization of a Horizontally Partitioned, High-Speed, 3D Tree-Based FPGA. - Vinod Pangracious; Zied Marrakchi; Habib Mehrez (IEEE Micro, 2015)

Three-Dimensional Design Methodologies for Tree-based FPGA Architecture - Vinod Pangracious; Zied Marrakchi; Habib Mehrez (Springer, 2015)

Using Timing-Driven Inter-FPGA Routing for Multi-FPGA Prototyping Exploration. - Umer Farooq 001; Roselyne Chotin-Avot; Muhammad Moazam Azeem; Zouha Cherif; Maminionja Ravoson; Saqib Khan; Habib Mehrez (DSD, 2016)

AEGIS-Based Efficient Solution for Secure Reconfiguration of FPGAs. - Karim M. Abdellatif; Roselyne Chotin-Avot; Habib Mehrez (CS2@HiPEAC, 2016)

Multiple FPGAs based prototyping and debugging with complete design flow. - Muhammad Moazam Azeem; Roselyne Chotin-Avot; Umer Farooq 001; Maminionja Ravoson; Habib Mehrez (IDT, 2016)

Design of advanced 2D and 3D FPGAs: Architecture-level exploration and algorithm-level optimization. - Sonda Chtourou; Mohamed Abid; Zied Marrakchi; Emna Amouri; Habib Mehrez (IDT, 2016)

The effect of interconnect depopulation on FPGA performances in terms of power, area and delay. - Sonda Chtourou; Mohamed Abid; Zied Marrakchi; Emna Amouri; Habib Mehrez (HPCS, 2016)

Exploration of Mesh-Based FPGA Architecture: Comparison of 2D and 3D Technologies in Terms of Power, Area and Performance. - Sonda Chtourou; Zied Marrakchi; Emna Amouri; Vinod Pangracious; Habib Mehrez; Mohamed Abid (PDP, 2016)

Inter-FPGA routing environment for performance exploration of multi-FPGA systems. - Umer Farooq 001; Roselyne Chotin-Avot; Muhammad Moazam Azeem; Maminionja Ravoson; Mariem Turki; Habib Mehrez (RSP, 2016)

Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires. - Sonda Chtourou; Zied Marrakchi; Emna Amouri; Vinod Pangracious; Mohamed Abid; Habib Mehrez (Microprocess. Microsystems, 2016)

On Exploiting Partitioning-Based Placement Approach for Performances Improvement of 3D FPGA. - Sonda Chtourou; Mohamed Abid; Zied Marrakchi; Emna Amouri; Habib Mehrez (HPCS, 2017)

Comparison of direct and switch-based inter-FPGA routing interconnect for multi-FPGA systems. - Umer Farooq 001; Habib Mehrez; Muhammad Khurram Bhatti (ReConFig, 2017)

Performance analysis and optimization of cluster-based mesh FPGA architectures: design methodology and CAD tool support. - Sonda Chtourou; Zied Marrakchi; Emna Amouri; Vinod Pangracious; Mohamed Abid; Habib Mehrez (Turkish J. Electr. Eng. Comput. Sci., 2017)

AES-GCM and AEGIS: Efficient and High Speed Hardware Implementations. - Karim M. Abdellatif; Roselyne Chotin-Avot; Habib Mehrez (J. Signal Process. Syst., 2017)

Inter-FPGA interconnect topologies exploration for multi-FPGA systems. - Umer Farooq 001; Habib Mehrez; Muhammad Khurram Bhatti (Des. Autom. Embed. Syst., 2018)

Novel architectural space exploration environment for multi-FPGA based prototyping systems. - Umer Farooq 001; Roselyne Chotin-Avot; Muhammad Moazam Azeem; Maminionja Ravoson; Habib Mehrez (Microprocess. Microsystems, 2018)

Pre-Silicon Verification Using Multi-FPGA Platforms: A Review. - Umer Farooq 001; Habib Mehrez (J. Electron. Test., 2021)

Prototyping using multi-FPGA platform: A novel and complete flow. - Umer Farooq 001; Imran Baig; Muhammad Khurram Bhatti; Habib Mehrez; Arun Kumar 014; Manoj Gupta (Microprocess. Microsystems, 2023)