Intelligent String Search Processor to Accelerate Text Information Retrieval. - Kousuke Takahashi; Hachiro Yamada; Hajime Nagai; Masaki Hirata (IWDM, 1987)

A versatile data string-search VLSI. - Masaki Hirata; Hachiro Yamada; Hajime Nagai; Kousuke Takahashi (IEEE J. Solid State Circuits, 1988)

A 200-MHz 16-bit super high-speed signal processor (SSSP) LSI. - Masakazu Yamashina; Junichi Goto; Fuyuki Okamoto; Koichi Ando; Hachiro Yamada; Tadahiko Horiuchi; Kimiko Nakamura; Tadayoshi Enomoto (IEEE J. Solid State Circuits, 1989)

A 1.2-million transistor, 33-MHz, 20-b dictionary search processor (DISP) ULSI with a 160-kb CAM. - Masato Motomura; Jun Toyoura; Kazumi Hirata; Hideyuki Ooka; Hachiro Yamada; Tadayoshi Enomoto (IEEE J. Solid State Circuits, 1990)

250-MHz BiCMOS super-high-speed video signal processor (S-VSP) ULSI. - Junichi Goto; Koichi Ando; Toshiaki Inoue; Masakazu Yamashina; Hachiro Yamada; Tadayoshi Enomoto (IEEE J. Solid State Circuits, 1991)

A 200-MFLOPS 100-MHz 64-b BiCMOS vector-pipelined processor (VPP) ULSI. - Fuyuki Okamoto; Yasuhiko Hagihara; Chie Ohkubo; Naoki Nishi; Hachiro Yamada; Tadayoshi Enomoto (IEEE J. Solid State Circuits, 1991)

A 2 K-word dictionary search processor (DISP) LSI with an approximate word search capability. - Masato Motomura; Hachiro Yamada; Tadayoshi Enomoto (IEEE J. Solid State Circuits, 1992)

A 300-MHz 16-b BiCMOS video signal processor. - Toshiaki Inoue; Junichi Goto; Masakazu Yamashina; Kazumasa Suzuki; Masahiro Nomura; Youichi Koseki; Tohru Kimura; Takao Atsumo; Masato Motomura; Benjamin S. Shih; Tadahiko Horiuchi; Nobuhisa Hamatake; et al. (IEEE J. Solid State Circuits, 1993)

A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI. - Masahiro Nomura; Masakazu Yamashina; Junichi Goto; Toshiaki Inoue; Kazumasa Suzuki; Masato Motomura; Youichi Koseki; Benjamin S. Shih; Tadahiko Horiuchi; Nobuhisa Hamatake; Kouichi Kumagai; Tadayoshi Enomoto; et al. (IEEE J. Solid State Circuits, 1994)

A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor. - Kazumasa Suzuki; Masakazu Yamashina; Takashi Nakayama; Masanori Izumikawa; Masahiro Nomura; Hiroyuki Igura; Hideki Heiuchi; Junichi Goto; Toshiaki Inoue; Youichi Koseki; Hitoshi Abiko; Kazuhiro Okabe; et al. (IEEE J. Solid State Circuits, 1994)

Cache-processor coupling: a fast and wide on-chip data cache design. - Masato Motomura; Toshiaki Inoue; Hachiro Yamada; Akihiko Konagaya (IEEE J. Solid State Circuits, 1995)

A 1-Mb 2-Tr/b nonvolatile CAM based on flash memory technologies. - Tohru Miwa; Hachiro Yamada; Yoshinori Hirota; Toshiya Satoh; Hideki Hara (IEEE J. Solid State Circuits, 1996)

A GHz MOS adaptive pipeline technique using MOS current-mode logic. - Masayuki Mizuno; Masakazu Yamashina; Koichiro Furuta; Hiroyuki Igura; Hitoshi Abiko; Kazuhiro Okabe; Atsuki Ono; Hachiro Yamada (IEEE J. Solid State Circuits, 1996)

Floating-point datapaths with online built-in self speed test. - Yasuhiko Hagihara; Shigeto Inui; Fuyuki Okamoto; Masato Nishida; Toshihiko Nakamura; Hachiro Yamada (IEEE J. Solid State Circuits, 1997)