A Novel Merged Multiplier-Accumulator Embedded in DSP Coprocessor. - Hadi Parandeh-Afshar; Mohsen Ahmadvand; Saeed Safari (ICECS, 2006)

A very high performance address BUS encoder. - Hadi Parandeh-Afshar; Ali Afzali-Kusha; Ali Khaki-Firooz (ISCAS, 2006)

Enhancing FPGA Performance for Arithmetic Circuits. - Philip Brisk; Ajay Kumar Verma; Paolo Ienne; Hadi Parandeh-Afshar (DAC, 2007)

Fast INC-XOR codec for low-power address buses. - Hadi Parandeh-Afshar; Mohsen Saneei; Ali Afzali-Kusha; Massoud Pedram (IET Comput. Digit. Tech., 2007)

Efficient synthesis of compressor trees on FPGAs. - Hadi Parandeh-Afshar; Philip Brisk; Paolo Ienne (ASP-DAC, 2008)

Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming. - Hadi Parandeh-Afshar; Philip Brisk; Paolo Ienne (DATE, 2008)

Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs. - Alessandro Cevrero; Panagiotis Athanasopoulos; Hadi Parandeh-Afshar; Ajay Kumar Verma; Philip Brisk; Frank K. Gürkaynak; Yusuf Leblebici; Paolo Ienne (FPGA, 2008)

A novel FPGA logic block for improved arithmetic performance. - Hadi Parandeh-Afshar; Philip Brisk; Paolo Ienne (FPGA, 2008)

3D configuration caching for 2D FPGAs. - Alessandro Cevrero; Panagiotis Athanasopoulos; Hadi Parandeh-Afshar; Philip Brisk; Yusuf Leblebici; Paolo Ienne; Maurizio Skerlj (FPGA, 2009)

Using 3D integration technology to realize multi-context FPGAs. - Alessandro Cevrero; Panagiotis Athanasopoulos; Hadi Parandeh-Afshar; Maurizio Skerlj; Philip Brisk; Yusuf Leblebici; Paolo Ienne (FPL, 2009)

Exploiting fast carry-chains of FPGAs for designing compressor trees. - Hadi Parandeh-Afshar; Philip Brisk; Paolo Ienne (FPL, 2009)

A flexible DSP block to enhance FPGA arithmetic performance. - Hadi Parandeh-Afshar; Alessandro Cevrero; Panagiotis Athanasopoulos; Philip Brisk; Yusuf Leblebici; Paolo Ienne (FPT, 2009)

Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs. - Alessandro Cevrero; Panagiotis Athanasopoulos; Hadi Parandeh-Afshar; Ajay Kumar Verma; Seyed-Hosein Attarzadeh-Niaki; Chrysostomos Nicopoulos; Frank K. Gürkaynak; Philip Brisk; Yusuf Leblebici; Paolo Ienne (ACM Trans. Reconfigurable Technol. Syst., 2009)

An FPGA Logic Cell and Carry Chain Configurable as a 6: 2 or 7: 2 Compressor. - Hadi Parandeh-Afshar; Philip Brisk; Paolo Ienne (ACM Trans. Reconfigurable Technol. Syst., 2009)

Highly Versatile DSP Blocks for Improved FPGA Arithmetic Performance. - Hadi Parandeh-Afshar; Paolo Ienne (FCCM, 2010)

Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic. - Amit Verma 002; Ajay Kumar Verma; Hadi Parandeh-Afshar; Philip Brisk; Paolo Ienne (FPL, 2010)

Improving FPGA Performance for Carry-Save Arithmetic. - Hadi Parandeh-Afshar; Ajay Kumar Verma; Philip Brisk; Paolo Ienne (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Reducing the pressure on routing resources of FPGAs with generic logic chains. - Hadi Parandeh-Afshar; Grace Zgheib; Philip Brisk; Paolo Ienne (FPGA, 2011)

Measuring and Reducing the Performance Gap between Embedded and Soft Multipliers on FPGAs. - Hadi Parandeh-Afshar; Paolo Ienne (FPL, 2011)

Compressor tree synthesis on commercial high-performance FPGAs. - Hadi Parandeh-Afshar; Arkosnato Neogy; Philip Brisk; Paolo Ienne (ACM Trans. Reconfigurable Technol. Syst., 2011)

Reducing the cost of floating-point mantissa alignment and normalization in FPGAs. - Yehdhih Ould Mohammed Moctar; Nithin George; Hadi Parandeh-Afshar; Paolo Ienne; Guy G. F. Lemieux; Philip Brisk (FPGA, 2012)

Rethinking FPGAs: elude the flexibility excess of LUTs with and-inverter cones. - Hadi Parandeh-Afshar; Hind Benbihi; David Novo; Paolo Ienne (FPGA, 2012)

Closing the Gap between FPGA and ASIC - Balancing Flexibility and Efficiency. - Hadi Parandeh-Afshar (2012)

Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only). - Hadi Parandeh-Afshar; Grace Zgheib; David Novo; Madhura Purnaprajna; Paolo Ienne (FPGA, 2013)

Shadow And-Inverter Cones. - Hadi Parandeh-Afshar; Grace Zgheib; David Novo; Madhura Purnaprajna; Paolo Ienne (FPL, 2013)

Revisiting and-inverter cones. - Grace Zgheib; Liqun Yang; Zhihong Huang; David Novo; Hadi Parandeh-Afshar; Haigang Yang; Paolo Ienne (FPGA, 2014)

CAL: Exploring cost, accuracy, and latency in approximate and speculative adder design. - Sina Boroumand; Hadi Parandeh-Afshar; Philip Brisk; Siamak Mohammadi (DFT, 2017)

Exploration of approximate multipliers design space using carry propagation free compressors. - Sina Boroumand; Hadi Parandeh-Afshar; Philip Brisk; Siamak Mohammadi (ASP-DAC, 2018)

Approximate quaternary addition with the fast carry chains of FPGAs. - Sina Boroumand; Hadi Parandeh-Afshar; Philip Brisk (DATE, 2018)