DDR SDRAM Memory Controller for Digital TV Decoders. - Hadley M. Siqueira; Ivan Saraiva Silva; Márcio Eduardo Kreutz; Edgard de Faria Corrêa (SBESC, 2011)

A Complete H.264 Motion Estimation Architecture. - Hadley M. Siqueira; Alba Sandyra Bezerra Lopes; Victor Marinho; Edgard de Faria Corrêa (SBESC, 2012)

A Coarse-Grained Reconfigurable Architecture for a PRET Machine. - Hadley M. Siqueira; Márcio Eduardo Kreutz (SBESC, 2018)

A simultaneous multithreading processor architecture with predictable timing behavior. - Hadley M. Siqueira; Márcio Eduardo Kreutz (Des. Autom. Embed. Syst., 2020)

AccPRET: a proposal of a multicore architecture with reconfigurable accelerators and time predictability. - Hadley M. Siqueira; Márcio Eduardo Kreutz (J. Supercomput., 2025)