Haechang Lee

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.

Known people with the same name:

Bibliography

2023
Automotive 2.1 μm Full-Depth Deep Trench Isolation CMOS Image Sensor with a 120 dB Single-Exposure Dynamic Range.
Sensors, November, 2023

2017
A 36-V 49% Efficient Hybrid Charge Pump in Nanometer-Scale Bulk CMOS Technology.
IEEE J. Solid State Circuits, 2017

2015
A 3 ppm 1.5 × 0.8 mm 2 1.0 µA 32.768 kHz MEMS-Based Oscillator.
IEEE J. Solid State Circuits, 2015


2014
23.8 A 34V charge pump in 65nm bulk CMOS technology.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

12.9 A 1.55×0.85mm<sup>2</sup> 3ppm 1.0μA 32.768kHz MEMS-based oscillator.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

2013
A Temperature-to-Digital Converter for a MEMS-Based Programmable Oscillator With < ±0.5-ppm Frequency Stability and < 1-ps Integrated Jitter.
IEEE J. Solid State Circuits, 2013

2012
A temperature-to-digital converter for a MEMS-based programmable oscillator with better than ±0.5ppm frequency stability.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2011
Analog-DFE-based 16Gb/s SerDes in 40nm CMOS that operates across 34dB loss channels at Nyquist with a baud rate CDR and 1.2Vpp voltage-mode driver.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
Low-skew clock distribution using zero-phase-clock-buffer DLLs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2009
A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface.
IEEE J. Solid State Circuits, 2009

2008
Near-Optimal Equalizer and Timing Adaptation for I/O Links Using a BER-Based Metric.
IEEE J. Solid State Circuits, 2008

Clocking circuits for a 16Gb/s memory interface.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

2006
Improving CDR Performance via Estimation.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006


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