A high-speed CMOS comparator for use in an ADC. - Benjamin J. McCarroll; Charles G. Sodini; Hae-Seung Lee (IEEE J. Solid State Circuits, 1988)

A digital readout technique for capacitive sensor applications. - Joseph T. Kung; Hae-Seung Lee; Roger T. Howe (IEEE J. Solid State Circuits, 1988)

The effects of oxide traps on the large-signal transient response of analog MOS circuits. - Theodore L. Tewksbury; Hae-Seung Lee; Gerald A. Miller (IEEE J. Solid State Circuits, 1989)

A 200-MHz CMOS phase-locked loop with dual phase detectors. - Kurt M. Ware; Hae-Seung Lee; Charles G. Sodini (IEEE J. Solid State Circuits, 1989)

A high-frequency fully differential BiCMOS operational amplifier. - Andrew N. Karanicolas; Kenneth K. O; John Y. A. Wang; Hae-Seung Lee; Rafael L. Reif (IEEE J. Solid State Circuits, 1991)

Analog VLSI systems for image acquisition and fast early vision processing. - John L. Wyatt Jr.; Craig L. Keast; Mark Seidel; David L. Standley; Berthold K. P. Horn; Tom Knight; Charles G. Sodini; Hae-Seung Lee; Tomaso A. Poggio (Int. J. Comput. Vis., 1992)

CMOS resistive fuses for image smoothing and segmentation. - Paul C. Yu; Steven J. Decker; Hae-Seung Lee; Charles G. Sodini; John L. Wyatt Jr. (IEEE J. Solid State Circuits, 1992)

A 40*40 CCD/CMOS absolute-value-of-difference processor for use in a stereo vision system. - J. Mikko Hakkarainen; Hae-Seung Lee (IEEE J. Solid State Circuits, 1993)

A 15-b 1-Msample/s digitally self-calibrated pipeline ADC. - Andrew N. Karanicolas; Hae-Seung Lee; Kantilal L. Barcrania (IEEE J. Solid State Circuits, 1993)

A high-swing 2-V CMOS operational amplifier with replica-amp gain enhancement. - Paul C. Yu; Hae-Seung Lee (IEEE J. Solid State Circuits, 1993)

Characterization, modeling, and minimization of transient threshold voltage shifts in MOSFETs. - Theodore L. Tewksbury; Hae-Seung Lee (IEEE J. Solid State Circuits, 1994)

A 300-MHz BiCMOS serial data transceiver. - Barry Thompson; Hae-Seung Lee; Lawrence M. DeVito (IEEE J. Solid State Circuits, 1994)

A 12-b 600 ks/s digitally self-calibrated pipelined algorithmic ADC. - Hae-Seung Lee (IEEE J. Solid State Circuits, 1994)

16-channel oversampled analog-to-digital converter. - S. Nadeem 002; Charles G. Sodini; Hae-Seung Lee (IEEE J. Solid State Circuits, 1994)

A 9-b charge-to-digital converter for integrated image sensors. - Susanne A. Paul; Hae-Seung Lee (IEEE J. Solid State Circuits, 1996)

A 2.5-V, 12-b, 5-MSample/s pipelined CMOS ADC. - Paul C. Yu; Hae-Seung Lee (IEEE J. Solid State Circuits, 1996)

Estimating the Focus of Expansion in Analog VLSI. - Ignacio S. McQuirk; Berthold K. P. Horn; Hae-Seung Lee; John L. Wyatt Jr. (Int. J. Comput. Vis., 1998)

A high-swing CMOS telescopic operational amplifier. - Kush Gulati; Hae-Seung Lee (IEEE J. Solid State Circuits, 1998)

A mixed-signal array processor with early vision applications. - David A. Martin; Hae-Seung Lee; Ichiro Masaki (IEEE J. Solid State Circuits, 1998)

A Nyquist-rate pipelined oversampling A/D converter. - Susanne A. Paul; Hae-Seung Lee; John Goodrich; Titiimaea F. Alailima; Daniel D. Santiago (IEEE J. Solid State Circuits, 1999)

Corrections to "a high-swing CMOS telescopic operational amplifier". - Kush Gulati; Hae-Seung Lee (IEEE J. Solid State Circuits, 2000)

A low-power reconfigurable analog-to-digital converter. - Kush Gulati; Hae-Seung Lee (IEEE J. Solid State Circuits, 2001)

Superconducting bandpass ΔΣ modulator with 2.23-GHz center frequency and 42.6-GHz sampling rate. - John F. Bulzacchelli; Hae-Seung Lee; James A. Misewich; Mark B. Ketchen (IEEE J. Solid State Circuits, 2002)

Oversampled pipeline A/D converters with mismatch shaping. - Ayman Shabra; Hae-Seung Lee (IEEE J. Solid State Circuits, 2002)

A 942 MHz output, 17.5 MHz bandwidth, -70dBc IMD3 ΣΔ DAC. - Susan Luschas; Richard Schreier; Hae-Seung Lee (CICC, 2003)

Output impedance requirements for DACs. - Susan Luschas; Hae-Seung Lee (ISCAS (1), 2003)

Radio frequency digital-to-analog converter. - Susan Luschas; Richard Schreier; Hae-Seung Lee (IEEE J. Solid State Circuits, 2004)

Study of substrate noise and techniques for minimization. - Mark Shane Peng; Hae-Seung Lee (IEEE J. Solid State Circuits, 2004)

CMOS-based microdisplay with calibrated backplane. - Andrew R. Chen; Akintunde Ibitayo (Tayo) Akinwande; Hae-Seung Lee (IEEE J. Solid State Circuits, 2005)

A 3MPixel Low-Noise Flexible Architecture CMOS Image Sensor. - Jungwook Yang; Keith Fife; Lane Brooks; Charles G. Sodini; Andrew Betts; Pavan Mudunuru; Hae-Seung Lee (ISSCC, 2006)

Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies. - John Kenneth Fiorenza; Todd Sepke; Peter Holloway; Charles G. Sodini; Hae-Seung Lee (IEEE J. Solid State Circuits, 2006)

A 14-b 30MS/s 0.75mm2 Pipelined ADC with On-Chip Digital Self-Calibration. - Ho-Young Lee; Tae-Hwan Oh; Ho-Jin Park; Hae-Seung Lee; Mark Spaeth; Jae-Whui Kim (CICC, 2007)

Transient Noise Analysis for Comparator-Based Switched-Capacitor Circuits. - Albert Chow; Hae-Seung Lee (ISCAS, 2007)

A Zero-Crossing-Based 8b 200MS/s Pipelined ADC. - Lane Brooks; Hae-Seung Lee (ISSCC, 2007)

A Zero-Crossing-Based 8-bit 200 MS/s Pipelined ADC. - Lane Brooks; Hae-Seung Lee (IEEE J. Solid State Circuits, 2007)

A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control. - Moo-Yeol Choi; Sung-No Lee; Seung-Bin You; Wang-Seup Yeum; Ho-Jin Park; Jae-Whui Kim; Hae-Seung Lee (CICC, 2008)

A 16b 10MS/s digitally self-calibrated ADC with time constant control. - Tae-Hwan Oh; Ho-Young Lee; Ju-Hwa Kim; Ho-Jin Park; Kyoung-Ho Moon; Jae-Whui Kim; Hae-Seung Lee (CICC, 2008)

Analog-to-Digital Converters: Digitizing the Analog World. - Hae-Seung Lee; Charles G. Sodini (Proc. IEEE, 2008)

Background Calibration of Pipelined ADCs Via Decision Boundary Gap Estimation. - Lane Brooks; Hae-Seung Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2008)

Digital Background Calibration in Pipelined ADCs Using Commutated Feedback Capacitor Switching. - Nan Sun 003; Hae-Seung Lee; Donhee Ham (IEEE Trans. Circuits Syst. II Express Briefs, 2008)

A 12b 50MS/s fully differential zero-crossing-based ADC without CMFB. - Lane Brooks; Hae-Seung Lee (ISSCC, 2009)

A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC. - Lane Brooks; Hae-Seung Lee (IEEE J. Solid State Circuits, 2009)

Noise Analysis for Comparator-Based Circuits. - Todd Sepke; Peter Holloway; Charles G. Sodini; Hae-Seung Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2009)

Offset cancellation for zero crossing based circuits. - Albert Chow; Hae-Seung Lee (ISCAS, 2010)

Zero-Crossing-Based Ultra-Low-Power A/D Converters. - Hae-Seung Lee; Lane Brooks; Charles G. Sodini (Proc. IEEE, 2010)

A 450 MS/s 10-bit time-interleaved zero-crossing based ADC. - Jack Chu; Hae-Seung Lee (CICC, 2011)

A 12b 5-to-50MS/s 0.5-to-1V voltage scalable zero-crossing based pipelined ADC. - Sunghyuk Lee; Anantha P. Chandrakasan; Hae-Seung Lee (ESSCIRC, 2011)

Redundancy in SAR ADCs. - Albert H. Chang; Hae-Seung Lee; Duane S. Boning (ACM Great Lakes Symposium on VLSI, 2011)

Zero-Crossing Detector Based Reconfigurable Analog System. - Payam Lajevardi; Anantha P. Chandrakasan; Hae-Seung Lee (IEEE J. Solid State Circuits, 2011)

A 12b 200MS/s frequency scalable zero-crossing based pipelined ADC in 55nm CMOS. - Soon-Kyun Shin; Jacques Christophe Rudell; Denis C. Daly; Carlos E. Muñoz; Dong-Young Chang; Kush Gulati; Hae-Seung Lee; Matthew Z. Straayer (CICC, 2012)

A 2.9-mW 11-b 20-MS/s pipelined ADC with dual-mode-based digital background calibration. - Nan Sun 003; Hae-Seung Lee; Donhee Ham (ESSCIRC, 2012)

A 12 b 5-to-50 MS/s 0.5-to-1 V Voltage Scalable Zero-Crossing Based Pipelined ADC. - Sunghyuk Lee; Anantha P. Chandrakasan; Hae-Seung Lee (IEEE J. Solid State Circuits, 2012)

A 12b 50MS/s 2.1mW SAR ADC with redundancy and digital background calibration. - Albert H. Chang; Hae-Seung Lee; Duane S. Boning (ESSCIRC, 2013)

Power-efficient amplifier frequency compensation for continuous-time delta-sigma modulators. - Do-Yeon Yoon; Hae-Seung Lee; Jeffrey Gealow (MWSCAS, 2013)

Ultrasonic Imaging Transceiver Design for CMUT: A Three-Level 30-Vpp Pulse-Shaping Pulser With Improved Efficiency and a Noise-Optimized Receiver. - Kailiang Chen; Hae-Seung Lee; Anantha P. Chandrakasan; Charles G. Sodini (IEEE J. Solid State Circuits, 2013)

11.6 A 21mW 15b 48MS/s zero-crossing pipeline ADC in 0.13μm CMOS with 74dB SNDR. - Dong-Young Chang; Carlos E. Muñoz; Denis C. Daly; Soon-Kyun Shin; Kevin Guay; Thomas Thurston; Hae-Seung Lee; Kush Gulati; Matthew Z. Straayer (ISSCC, 2014)

22.4 A 1GS/s 10b 18.9mW time-interleaved SAR ADC with background timing-skew calibration. - Sunghyuk Lee; Anantha P. Chandrakasan; Hae-Seung Lee (ISSCC, 2014)

A Column-Row-Parallel ASIC architecture for 3D wearable / portable medical ultrasonic imaging. - Kailiang Chen; Hae-Seung Lee; Charles G. Sodini (VLSIC, 2014)

A 1 GS/s 10b 18.9 mW Time-Interleaved SAR ADC With Background Timing Skew Calibration. - Sunghyuk Lee; Anantha P. Chandrakasan; Hae-Seung Lee (IEEE J. Solid State Circuits, 2014)

A 12 bit 200 MS/s Zero-Crossing-Based Pipelined ADC With Early Sub-ADC Decision and Output Residue Background Calibration. - Soon-Kyun Shin; Jacques Christophe Rudell; Denis C. Daly; Carlos E. Muñoz; Dong-Young Chang; Kush Gulati; Hae-Seung Lee; Matthew Z. Straayer (IEEE J. Solid State Circuits, 2014)

A 200-MS/s 98-dB SNR track-and-hold in 0.25-um GaN HEMT. - SungWon Chung; Hae-Seung Lee (CICC, 2015)

Carotid arterial blood pressure waveform monitoring using a portable ultrasound system. - Joohyun Seo; Sabino J. Pietrangelo; Hae-Seung Lee; Charles G. Sodini (EMBC, 2015)

15.6 12b 250MS/S pipelined ADC with virtual ground reference buffers. - Hyun Ho Boo; Duane S. Boning; Hae-Seung Lee (ISSCC, 2015)

Session 26 overview: Nyquist-rate converters: Data converters subcommittee. - Hae-Seung Lee; Seng-Pan Li (ISSCC, 2015)

15.1 An 85dB-DR 74.6dB-SNDR 50MHZ-BW CT MASH ΔΣ modulator in 28nm CMOS. - Do-Yeon Yoon; Stacy Ho; Hae-Seung Lee (ISSCC, 2015)

A 12b 250 MS/s Pipelined ADC With Virtual Ground Reference Buffers. - Hyun Ho Boo; Duane S. Boning; Hae-Seung Lee (IEEE J. Solid State Circuits, 2015)

A Continuous-Time Sturdy-MASH ΔΣ Modulator in 28 nm CMOS. - Do-Yeon Yoon; Stacy Ho; Hae-Seung Lee (IEEE J. Solid State Circuits, 2015)

Data converter reflections: 19 papers from the last ten years that deserve a second look. - David Robertson 002; Aaron Buchwald; Michael Flynn; Hae-Seung Lee; Un-Ku Moon; Boris Murmann (ESSCIRC, 2016)

A Sampling Clock Skew Correction Technique for Time-Interleaved SAR ADCs. - Daniel Prashanth; Hae-Seung Lee (ACM Great Lakes Symposium on VLSI, 2016)

Design of a 4th-order multi-stage feedforward operational amplifier for continuous-time bandpass delta sigma modulators. - Xi Yang; Hae-Seung Lee (ISCAS, 2016)

A Column-Row-Parallel ASIC Architecture for 3-D Portable Medical Ultrasonic Imaging. - Kailiang Chen; Hae-Seung Lee; Charles G. Sodini (IEEE J. Solid State Circuits, 2016)

0.3 V ultra-low power sensor interface for EMG. - Sirma Orguc; Harneet Singh Khurana; Hae-Seung Lee; Anantha P. Chandrakasan (ESSCIRC, 2017)

EMG-based Real Time Facial Gesture Recognition for Stress Monitoring. - Sirma Orguc; Harneet Singh Khurana; Konstantina M. Stankovic; Hae-Seung Lee; Anantha P. Chandrakasan (EMBC, 2018)

Monitoring of Pulse Pressure and Arterial Pressure Waveform Changes during the Valsalva Maneuver by a Portable Ultrasound System. - Joohyun Seo; Charles G. Sodini; Hae-Seung Lee (EMBC, 2018)

Recode then LSB-first SAR ADC for Reducing Energy and Bit-cycles. - Harneet Singh Khurana; Anantha P. Chandrakasan; Hae-Seung Lee (ISCAS, 2018)

Design of a 6th-order Continuous-time Bandpass Delta-Sigma Modulator with 250 MHz IF, 25 MHz Bandwidth, and over 75 dB SNDR. - Xi Yang; Hae-Seung Lee (ISCAS, 2018)

Learning to Design Circuits. - Hanrui Wang 002; Jiacheng Yang; Hae-Seung Lee; Song Han 003 (CoRR, 2018)

An 8-bit 2.8 GS/s Flash ADC with Time-based Offset Calibration and Interpolation in 65 nm CMOS. - Xi Yang; Seung-Jun Bae; Hae-Seung Lee (ESSCIRC, 2019)

S2ADC: A 12-bit, 1.25MS/s Secure SAR ADC with Power Side-Channel Attack Resistance. - Taehoon Jeong; Anantha P. Chandrakasan; Hae-Seung Lee (CICC, 2020)

GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning. - Hanrui Wang 002; Kuan Wang; Jiacheng Yang; Linxiao Shen; Nan Sun 001; Hae-Seung Lee; Song Han 003 (DAC, 2020)

S2ADC: A 12-bit, 1.25-MS/s Secure SAR ADC With Power Side-Channel Attack Resistance. - Taehoon Jeong; Anantha P. Chandrakasan; Hae-Seung Lee (IEEE J. Solid State Circuits, 2021)

Non-Invasive Evaluation of a Carotid Arterial Pressure Waveform Using Motion-Tolerant Ultrasound Measurements During the Valsalva Maneuver. - Joohyun Seo; Hae-Seung Lee; Charles G. Sodini (IEEE J. Biomed. Health Informatics, 2021)

A Bit-level Sparsity-aware SAR ADC with Direct Hybrid Encoding for Signed Expressions for AIoT Applications. - Ruicong Chen; H. T. Kung 001; Anantha P. Chandrakasan; Hae-Seung Lee (ISLPED, 2022)

RaM-SAR: A Low Energy and Area Overhead, 11.3fJ/conv.-step 12b 25MS/s Secure Random-Mapping SAR ADC with Power and EM Side-channel Attack Resilience. - Ruicong Chen; Hanrui Wang 002; Anantha P. Chandrakasan; Hae-Seung Lee (VLSI Technology and Circuits, 2022)

Machine Learning for Arterial Blood Pressure Prediction. - Jessica Zheng; Hanrui Wang 002; Anand Chandrasekhar; Aaron D. Aguirre; Song Han 003; Hae-Seung Lee; Charles G. Sodini (CHIL, 2023)

Sniff-SAR: A 9.8fJ/c.-s 12b secure ADC with detectiondriven protection against power and EM side-channel attack. - Ruicong Chen; Anantha P. Chandrakasan; Hae-Seung Lee (CICC, 2023)

Modeling Analog-Digital-Converter Energy and Area for Compute-In-Memory Accelerator Design. - Tanner Andrulis; Ruicong Chen; Hae-Seung Lee; Joel S. Emer; Vivienne Sze (CoRR, 2024)

A 6.4-GS/s 1-GHz BW Continuous-Time Pipelined ADC With Time-Interleaved Sub-ADC-DAC Achieving 61.7-dB SNDR in 16-nm FinFET. - Rishabh Mittal; Hajime Shibata; Sharvil Patil; Erik Krommenhoek; Prawal Shrestha; Gabriele Manganaro; Anantha P. Chandrakasan; Hae-Seung Lee (IEEE J. Solid State Circuits, 2024)

Mitigation of Vertical Fixed Pattern Noise in CMOS Image Sensors through Analog Offset Dithering and Dynamic Clock Adjustment. - Jaejin Jung; Sungyong Kim; Shinhwan Lim; Kyoungmin Koh; Hae-Seung Lee (ISCAS, 2025)