25.3 A 1.35V 5.0Gb/s/pin GDDR5M with 5.4mW standby power and an error-adaptive duty-cycle corrector. - Hyun-Woo Lee; Junyoung Song; Sangah Hyun; Seunggeun Baek; Yuri Lim; Jungwan Lee; Minsu Park; Haerang Choi; Changkyu Choi; Jin-Youp Cha; Jaeil Kim; Hoon Choi; et al. (ISSCC, 2014)

A Novel In-DRAM Accelerator Architecture for Binary Neural Network. - Haerang Choi; Yosep Lee; Jae-Joon Kim; Sungjoo Yoo (COOL CHIPS, 2020)

McDRAM v2: In-Dynamic Random Access Memory Systolic Array Accelerator to Address the Large Model Problem in Deep Neural Networks on the Edge. - Seunghwan Cho; Haerang Choi; Eunhyeok Park; Hyunsung Shin; Sungjoo Yoo (IEEE Access, 2020)

Reducing DRAM refresh power consumption by runtime profiling of retention time and dual-row activation. - Haerang Choi; Do-sun Hong; Jaesung Lee; Sungjoo Yoo (Microprocess. Microsystems, 2020)

System Architecture and Software Stack for GDDR6-AiM. - Yongkee Kwon; Kornijcuk Vladimir; Nahsung Kim; Woojae Shin; Jongsoon Won; Minkyu Lee; Hyunha Joo; Haerang Choi; Guhyun Kim; Byeongju An; Jeongbin Kim 001; Jaewook Lee; et al. (HCS, 2022)

A 1ynm 1.25V 8Gb, 16Gb/s/pin GDDR6-based Accelerator-in-Memory supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep-Learning Applications. - Seong Ju Lee; Kyu-Young Kim; Sanghoon Oh; Joonhong Park; Gimoon Hong; Dong Yoon Ka; Kyu-Dong Hwang; Jeongje Park; Kyeong Pil Kang; Jungyeon Kim; Junyeol Jeon; Nahsung Kim; et al. (ISSCC, 2022)

Memory-Centric Computing with SK Hynix's Domain-Specific Memory. - Yongkee Kwon; Guhyun Kim; Nahsung Kim; Woojae Shin; Jongsoon Won; Hyunha Joo; Haerang Choi; Byeongju An; Gyeongcheol Shin; Dayeon Yun; Jeongbin Kim 001; Changhyun Kim; et al. (HCS, 2023)

Darwin: A DRAM-based Multi-level Processing-in-Memory Architecture for Data Analytics. - Donghyuk Kim; Jae-Young Kim; Wontak Han; Jongsoon Won; Haerang Choi; Yongkee Kwon; Joo-Young Kim 001 (CoRR, 2023)

A 1ynm 1.25V 8Gb 16Gb/s/Pin GDDR6-Based Accelerator-in-Memory Supporting 1TFLOPS MAC Operation and Various Activation Functions for Deep Learning Application. - Dae-Han Kwon; Seongju Lee; Kyuyoung Kim; Sanghoon Oh; Joonhong Park; Gimoon Hong; Dongyoon Ka; Kyu-Dong Hwang; Jeongje Park; Kyeong Pil Kang; Jungyeon Kim; Junyeol Jeon; et al. (IEEE J. Solid State Circuits, 2023)

IANUS: Integrated Accelerator based on NPU-PIM Unified Memory System. - Minseok Seo; Xuan Truong Nguyen; Seok Joong Hwang; Yongkee Kwon; Guhyun Kim; Chanwook Park; Ilkon Kim; Jaehan Park; Jeongbin Kim 001; Woojae Shin; Jongsoon Won; Haerang Choi; et al. (ASPLOS (3), 2024)

SK Hynix AI-Specific Computing Memory Solution: From AiM Device to Heterogeneous AiMX-xPU System for Comprehensive LLM Inference. - Guhyun Kim; Jinkwon Kim; Nahsung Kim; Woojae Shin; Jongsoon Won; Hyunha Joo; Haerang Choi; Byeongju An; Gyeongcheol Shin; Dayeon Yun; Jeongbin Kim 001; Changhyun Kim; et al. (HCS, 2024)

LoL-PIM: Long-Context LLM Decoding with Scalable DRAM-PIM System. - Hyucksung Kwon; Kyungmo Koo; Janghyeon Kim; Woongkyu Lee; Minjae Lee; Hyungdeok Lee; Yousub Jung; Jaehan Park; Yosub Song; Byeongsu Yang; Haerang Choi; Guhyun Kim; et al. (CoRR, 2024)