A leakage estimation and reduction technique for scaled CMOS logic circuits considering gate-leakage. - Hafijur Rahman; Chaitali Chakrabarti (ISCAS (2), 2004)

An Efficient Control Point Insertion Technique for Leakage Reduction of Scaled CMOS Circuits. - Hafijur Rahman; Chaitali Chakrabarti (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

Tripartite sub-image histogram equalization for slightly low contrast gray-tone image enhancement. - Hafijur Rahman; Gour Chandra Paul (Pattern Recognit., 2023)