Design of Multiple-Output Networks using Time Domain Multiplexing and Shared Multi-Terminal Multiple-Valued Decision Diagrams. - Hafiz Md. Hasan Babu; Tsutomu Sasao (ISMVL, 1998)

Shared Multiple-Valued Decision Diagrams for Multiple-Output Functions. - Hafiz Md. Hasan Babu; Tsutomu Sasao (ISMVL, 1999)

Representations of Multiple-Output Switching Functions Using Multiple-Valued Pseudo-Kronecker Decision Diagrams. - Hafiz Md. Hasan Babu; Tsutomu Sasao (ISMVL, 2000)

A Heuristic Approach for Design of Easily Testable PLAs Using Pass Transistor Logic. - Md. Rafiqul Islam 001; Hafiz Md. Hasan Babu; Mohammad Abdur Rahim Mustafa; Md. Sumon Shahriar (Asian Test Symposium, 2003)

Reversible Logic Synthesis for Minimization of Full-Adder Circuit. - Hafiz Md. Hasan Babu; Md. Rafiqul Islam 001; Ahsan Raja Chowdhury; Syed Mostahed Ali Chowdhury (DSD, 2003)

A Technique for Logic Design of Voltage-Mode Pass Transistor Based Multi-Valued Multiple-Output Logic Circuits. - Hafiz Md. Hasan Babu; Md. Rafiqul Islam 001; Amin Ahsan Ali; Mohammad Musa Salehin Akon (ISMVL, 2003)

Implementation of Multiple-Valued Flip-Flips Using Pass Transistor Logic. - Hafiz Md. Hasan Babu; Moinul Islam Zaber; Md. Mazder Rahman; Md. Rafiqul Islam 001 (DSD, 2004)

A heuristic approach to synthesize Boolean functions using TANT network. - Hafiz Md. Hasan Babu; Md. Rafiqul Islam 001; Rumana Nazmul; Md. Anwarul Haque; Ahsan Raja Chowdhury (ISCAS (2), 2004)

On the Minimization of Multiple-Valued Input Binary-Valued Output Functions. - Hafiz Md. Hasan Babu; Moinul Islam Zaber; Md. Rafiqul Islam 001; Md. Mazder Rahman (ISMVL, 2004)

Synthesis of Full-Adder Circuit Using Reversible Logic. - Hafiz Md. Hasan Babu; Md. Rafiqul Islam 001; Syed Mostahed Ali Chowdhury; Ahsan Raja Chowdhury (VLSI Design, 2004)

An Advanced Minimization Technique for Multiple Valued Multiple Output Logic Expressions Using LUT and Realization Using Current Mode CMOS. - Md. Sumon Shahriar; A. R. Mustafa; Chowdhury Farhan Ahmed; Abu Ahmed Ferdaus; A. N. M. Zaheduzzaman; Shahed Anwar; Hafiz Md. Hasan Babu (DSD, 2005)

Design of a Reversible Binary Coded Decimal Adder by Using Reversible 4-Bit Parallel Adder. - Hafiz Md. Hasan Babu; Ahsan Raja Chowdhury (VLSI Design, 2005)

Realization of Digital Fuzzy Operations Using Multi-Valued Fredkin Gates. - Amin Ahsan Ali; Hafiz Md. Hasan Babu; Ahsan Raja Chowdhury (CDES, 2006)

A New Approach to Synthesize Multiple-Output Functions Using Reversible Programmable Logic Array. - Ahsan Raja Chowdhury; Rumana Nazmul; Hafiz Md. Hasan Babu (VLSI Design, 2006)

Design of a compact reversible binary coded decimal adder circuit. - Hafiz Md. Hasan Babu; Ahsan Raja Chowdhury (J. Syst. Archit., 2006)

Minimization of CTS of k-CNOT Circuits for SSF and MSF Model. - Muhammad Ibrahim; Ahsan Raja Chowdhury; Hafiz Md. Hasan Babu (DFT, 2008)

A Novel Approach to Design BCD Adder and Carry Skip BCD Adder. - Ashis Kumer Biswas; Md. Mahmudul Hasan; Moshaddek Hasan; Ahsan Raja Chowdhury; Hafiz Md. Hasan Babu (VLSI Design, 2008)

Efficient approaches for designing reversible Binary Coded Decimal adders. - Ashis Kumer Biswas; Md. Mahmudul Hasan; Ahsan Raja Chowdhury; Hafiz Md. Hasan Babu (Microelectron. J., 2008)

An Efficient Design of a Reversible Barrel Shifter. - Irina Hashmi; Hafiz Md. Hasan Babu (VLSI Design, 2010)

Efficient Wrapper/TAM Co-Optimization for SOC Using Rectangle Packing - Md. Rafiqul Islam 001; Muhammad Rezaul Karim 001; Abdullah Al Mahmud 002; Md. Saiful Islam 003; Hafiz Md. Hasan Babu (CoRR, 2010)

Variable Block Carry Skip Logic using Reversible Gates - Md. Rafiqul Islam 001; Md. Saiful Islam 003; Muhammad Rezaul Karim 001; Abdullah Al Mahmud 002; Hafiz Md. Hasan Babu (CoRR, 2010)

Building Toffoli Network for Reversible Logic Synthesis Based on Swapping Bit Strings - Hafiz Md. Hasan Babu; Md. Saiful Islam 003; Md. Rafiqul Islam 001; Lafifa Jamal; Abu Ahmed Ferdaus; Muhammad Rezaul Karim 001; Abdullah Al Mahmud 002 (CoRR, 2010)

Wrapper/TAM Co-Optimization and Test Scheduling for SOCs Using Rectangle Bin Packing Considering Diagonal Length of Rectangles - Md. Rafiqul Islam 001; Muhammad Rezaul Karim 001; Abdullah Al Mahmud 002; Md. Saiful Islam 003; Hafiz Md. Hasan Babu (CoRR, 2010)

Wrapper/TAM Co-Optimization and constrained Test Scheduling for SOCs Using Rectangle Bin Packing - Hafiz Md. Hasan Babu; Md. Rafiqul Islam 001; Muhammad Rezaul Karim 001; Abdullah Al Mahmud 002; Md. Saiful Islam 003 (CoRR, 2010)

Realization of Reversible Logic in DNA Computing. - Ankur Sarker; Tanvir Ahmed; S. M. Mahbubur Rashid; Shahed Anwar; Lafifa Jamal; Nazma Tara; Md. Masbaul Alam; Hafiz Md. Hasan Babu (BIBE, 2011)

An efficient approach for designing and minimizing reversible programmable logic arrays. - Sajib Kumar Mitra; Lafifa Jamal; Mineo Kaneko; Hafiz Md. Hasan Babu (ACM Great Lakes Symposium on VLSI, 2012)

On the Compact Designs of Low Power Reversible Decoders and Sequential Circuits. - Lafifa Jamal; Md. Masbaul Alam Polash; M. A. Mottalib; Hafiz Md. Hasan Babu (VDAT, 2012)

Implementation of reversible multiplier circuit using Deoxyribonucleic acid. - Ankur Sarker; Mohd. Istiaq Sharif; S. M. Mahbubur Rashid; Hafiz Md. Hasan Babu (BIBE, 2013)

Efficient approaches to design a reversible floating point divider. - Lafifa Jamal; Hafiz Md. Hasan Babu (ISCAS, 2013)

A novel approach to design a reversible shifter circuit using DNA. - Tanvir Ahmed; Ankur Sarker; Mohd. Istiaq Sharif; S. M. Mahbubur Rashid; Md. Atiqur Rahman; Hafiz Md. Hasan Babu (SoCC, 2013)

An efficient approach for designing a reversible fault tolerant n-bit carry look-ahead adder. - Hafiz Md. Hasan Babu; Lafifa Jamal; Nazir Saleheen (SoCC, 2013)

An optimal design of a fault tolerant reversible multiplier. - Lafifa Jamal; Md. Mushfiqur Rahman; Hafiz Md. Hasan Babu (SoCC, 2013)

A Low Power Fault Tolerant Reversible Decoder Using MOS Transistors. - Md. Shamsujjoha; Hafiz Md. Hasan Babu (VLSI Design, 2013)

Design of a Fault Tolerant Reversible Compact Unidirectional Barrel Shifter. - Md. Shamsujjoha; Hafiz Md. Hasan Babu; Lafifa Jamal; Ahsan Raja Chowdhury (VLSI Design, 2013)

Design of a compact reversible fault tolerant field programmable gate array: A novel approach in reversible logic synthesis. - Md. Shamsujjoha; Hafiz Md. Hasan Babu; Lafifa Jamal (Microelectron. J., 2013)

An efficient approach to design a reversible control unit of a processor. - Lafifa Jamal; Md. Masbaul Alam; Hafiz Md. Hasan Babu (Sustain. Comput. Informatics Syst., 2013)

A compact realization of an n-bit quantum carry skip adder circuit with optimal delay. - Nusrat Jahan Lisa; Hafiz Md. Hasan Babu (AHS, 2014)

A Cascading Wavelet-Feed Forward Neural Network Approach for Forecasting Traffic Flow. - Md. Mostafizur Rahman; Atsuhiro Takasu; Hafiz Md. Hasan Babu (EDBT/ICDT Workshops, 2014)

A novel approach to perform reversible addition/subtraction operations using deoxyribonucleic acid. - Ankur Sarker; Hafiz Md. Hasan Babu; Md. Saiful Islam 003 (ISCAS, 2014)

Minimization of a reversible quantum 2n-to-n BCD priority encoder. - Nusrat Jahan Lisa; Hafiz Md. Hasan Babu (NANOARCH, 2014)

Approach to design a compact reversible low power binary comparator. - Hafiz Md. Hasan Babu; Nazir Saleheen; Lafifa Jamal; Sheikh Muhammad Sarwar; Tsutomu Sasao (IET Comput. Digit. Tech., 2014)

A compact representation of a quantum controlled ternary barrel shifter. - Nusrat Jahan Lisa; Hafiz Md. Hasan Babu (ISCAS, 2015)

Design of a Compact Ternary Parallel Adder/Subtractor Circuit in Quantum Computing. - Nusrat Jahan Lisa; Hafiz Md. Hasan Babu (ISMVL, 2015)

Design and Implementation of a Reversible Central Processing Unit. - Lafifa Jamal; Hafiz Md. Hasan Babu (ISVLSI, 2015)

An Efficient Design of a Reversible Fault Tolerant n -to-2 ^n Sequence Counter Using Nano Meter MOS Transistors. - Md. Shamsujjoha; Sirin Nahar Sathi; Golam Sorwar; Fahmida Hossain; Md. Nawab Yousuf Ali; Hafiz Md. Hasan Babu (ICSI (3), 2015)

Design of a Compact Reversible Carry Look-Ahead Adder Using Dynamic Programming. - Nusrat Jahan Lisa; Hafiz Md. Hasan Babu (VLSID, 2015)

An efficient design technique of a quantum divider circuit. - Sayanton Vhaduri Dibbo; Hafiz Md. Hasan Babu; Lafifa Jamal (ISCAS, 2016)

Design of an optimized reversible bidirectional barrel shifter. - Sadia Nowrin; Lafifa Jamal; Hafiz Md. Hasan Babu (ISCAS, 2016)

A LUT-based matrix multiplication using neural networks. - Zarrin Tasnim Sworna; Mubin Ul Haque; Hafiz Md. Hasan Babu (ISCAS, 2016)

An Improved Design of a Reversible Fault Tolerant LUT-based FPGA. - Mubin Ul Haque; Zarrin Tasnim Sworna; Hafiz Md. Hasan Babu (VLSID, 2016)

Logic Synthesis in Reversible PLA. - Nazma Tara; Hafiz Md. Hasan Babu; Nawshi Matin (VLSID, 2016)

Low-power and area efficient binary coded decimal adder design using a look up table-based field programmable gate array. - Zarrin Tasnim Sworna; Mubin Ul Haque; Nazma Tara; Hafiz Md. Hasan Babu; Ashis Kumer Biswas (IET Circuits Devices Syst., 2016)

Design of a compact reversible fault tolerant division circuit. - Hafiz Md. Hasan Babu; Md. Solaiman Mia (Microelectron. J., 2016)

Area and Delay Efficient Design of a Quantum Bit String Comparator. - Hafiz Md. Hasan Babu; Lafifa Jamal; Sayanton Vhaduri Dibbo; Ashis Kumer Biswas (ISVLSI, 2017)

An Efficient Design of an FPGA-Based Multiplier Using LUT Merging Theorem. - Zarrin Tasnim Sworna; Mubin Ul Haque; Hafiz Md. Hasan Babu; Lafifa Jamal; Ashis Kumer Biswas (ISVLSI, 2017)

Efficient Techniques for Fault Detection and Correction of Reversible Circuits. - Hafiz Md. Hasan Babu; Md. Solaiman Mia; Ashis Kumer Biswas (J. Electron. Test., 2017)

Cost-efficient design of a quantum multiplier-accumulator unit. - Hafiz Md. Hasan Babu (Quantum Inf. Process., 2017)

Power efficient optimum design of the Reversible Plessey Logic Block of a field-programmable gate array. - Nazma Tara; Hafiz Md. Hasan Babu; Lafifa Jamal (Sustain. Comput. Informatics Syst., 2017)

A Fast FPGA-Based BCD Adder. - Mubin Ul Haque; Zarrin Tasnim Sworna; Hafiz Md. Hasan Babu; Ashis Kumer Biswas (Circuits Syst. Signal Process., 2018)

Quantum Technology for Comparator Circuit. - Hafiz Md. Hasan Babu; Khandaker Mohammad Mohi Uddin; Rownak Borhan Himel; Nitish Biswas (ISQED, 2022)

BreastMultiNet: A multi-scale feature fusion method using deep neural network to detect breast cancer. - Md. Mahbubur Rahman; Md. Saikat Islam Khan; Hafiz Md. Hasan Babu (Array, 2022)

A Cost-Efficient Look-Up Table Based Binary Coded Decimal Adder Design. - Zarrin Tasnim Sworna; Mubin Ul Haque; Hafiz Md. Hasan Babu; Lafifa Jamal (CoRR, 2022)

DNA Technology for Multi-Valued Data Storage using Read Only Memory. - Hafiz Md. Hasan Babu; Khandaker Mohammad Mohi Uddin; Tamanna Tabassum; Mohammed Nasir Uddin (FLAP, 2022)

Chi2-MI: A hybrid feature selection based machine learning approach in diagnosis of chronic kidney disease. - Samrat Kumar Dey; Khandaker Mohammad Mohi Uddin; Hafiz Md. Hasan Babu; Md. Mahbubur Rahman; Arpita Howlader; K. M. Aslam Uddin (Intell. Syst. Appl., 2022)

Prevention of shoulder-surfing attacks using shifting condition using digraph substitution rules. - Amanul Islam; Fazidah Othman; Nazmus Sakib; Hafiz Md. Hasan Babu (CoRR, 2023)

DNA Logic Design - Computing with DNA - Hafiz Md. Hasan Babu (DNA Logic Design, 2024)

A comprehensive approach to detecting chemical adulteration in fruits using computer vision, deep learning, and chemical sensors. - Abdus Sattar; Md. Asif Mahmud Ridoy; Aloke Kumar Saha; Hafiz Md. Hasan Babu; Mohammad Nurul Huda (Intell. Syst. Appl., 2024)