An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits. - Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (ASP-DAC, 1999)

A New Synthesis of Symmetric Functions. - Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (ASP-DAC/VLSI Design, 2002)

BIST Design for Detecting Multiple Stuck-Open Faults in CMOS Circuits Using Transition Count. - Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (J. Comput. Sci. Technol., 2002)

Mapping Symmetric Functions to Hierarchical Modules for Path-Delay Fault Testability. - Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (Asian Test Symposium, 2003)

A Simple Delay Testable Synthesis of Symmetric Functions. - Hafizur Rahaman 001; Debesh K. Das (AACC, 2004)

Testable design of GRM network with EXOR-tree for detecting stuck-at and bridging faults. - Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (ASP-DAC, 2004)

Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults. - Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (VLSI Design, 2004)

Bridging fault detection in Double Fixed-Polarity Reed-Muller (DFPRM) PLA. - Hafizur Rahaman 001; Debesh K. Das (ASP-DAC, 2005)

Cost Optimal Design of Nonlinear CA based PRPG for Test Applications. - Sukanta Das; Hafizur Rahaman 001; Biplab K. Sikdar (Asian Test Symposium, 2005)

Recent Trends in the Application of Meta-Heuristics to VLSI Layout Design. - Prasun Ghosal; Tuhina Samanta; Hafizur Rahaman 001; Parthasarathi Dasgupta (IICAI, 2005)

Easily Testable Implementation for Bit Parallel Multipliers in GF (2m). - Hafizur Rahaman 001; Jimson Mathew; Abusaleh M. Jabir; Dhiraj K. Pradhan (HLDVT, 2006)

A heuristic method for constructing hexagonal Steiner minimal trees for routing in VLSI. - Tuhina Samanta; Prasun Ghosal; Hafizur Rahaman 001; Parthasarathi Dasgupta (ISCAS, 2006)

An Energy Effilcient Monitoring of Ad-Hoc Sensor Network with Cellular Automata. - Indrajit Banerjee; Sukanta Das; Hafizur Rahaman 001; Biplab K. Sikdar (SMC, 2006)

Implementing Symmetric Functions with Hierarchical Modules for Stuck-At and Path-Delay Fault Testability. - Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (J. Electron. Test., 2006)

MDVM System Concept, Paging Latency and Round-2 Randomized Leader Election Algorithm in SG. - Susmit Bagchi; Hafizur Rahaman 001; Purnendu Das (J. Adv. Comput. Intell. Intell. Informatics, 2006)

Optimum Test Set for Bridging Fault Detection in Reversible Circuits. - Hafizur Rahaman 001; Dipak Kumar Kole; Debesh K. Das; Bhargab B. Bhattacharya (ATS, 2007)

Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test set. - Jimson Mathew; Hafizur Rahaman 001; Dhiraj K. Pradhan (IOLTS, 2007)

Minimum-Congestion Placement for Y-interconnects: Some studies and observations. - Tuhina Samanta; Prasun Ghosal; Hafizur Rahaman 001; Parthasarathi Dasgupta (ISVLSI, 2007)

Constant Function Independent Test Set for Fault Detection in Bit Parallel Multipliers in GF(2^m). - Hafizur Rahaman 001; Jimson Mathew; Dhiraj K. Pradhan (VLSI Design, 2007)

Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}). - Hafizur Rahaman 001; Jimson Mathew; Biplab K. Sikdar; Dhiraj K. Pradhan (VTS, 2007)

Accelerated Functional Testing of Digital Microfluidic Biochips. - Debasis Mitra 002; Sarmishtha Ghoshal; Hafizur Rahaman 001; Bhargab B. Bhattacharya; D. Dutta Majumder; Krishnendu Chakrabarty (ATS, 2008)

UDDN: Unidirectional Data Dissemination via Negotiation. - Indrajit Banerjee; Hafizur Rahaman 001 (ICOIN, 2008)

On Line Testing of Single Feedback Bridging Fault in Cluster Based FPGA by Using Asynchronous Element. - Nachiketa Das; Pranab Roy; Hafizur Rahaman 001 (IOLTS, 2008)

Thermal-Aware Placement of Standard Cells and Gate Arrays: Studies and Observations. - Prasun Ghosal; Tuhina Samanta; Hafizur Rahaman 001; Parthasarathi Dasgupta (ISVLSI, 2008)

Revisiting fidelity: a case of elmore-based Y-routing trees. - Tuhina Samanta; Prasun Ghosal; Hafizur Rahaman 001; Parthasarathi Dasgupta (SLIP, 2008)

Single Error Correcting Finite Field Multipliers Over GF(2m). - Jimson Mathew; Costas Argyrides; Abusaleh M. Jabir; Hafizur Rahaman 001; Dhiraj K. Pradhan (VLSI Design, 2008)

Design of Reversible Finite Field Arithmetic Circuits with Error Detection. - Jimson Mathew; Hafizur Rahaman 001; Babita R. Jose; Dhiraj K. Pradhan (VLSI Design, 2008)

A Galois Field Based Logic Synthesis Approach with Testability. - Jimson Mathew; Hafizur Rahaman 001; Ashutosh Kumar Singh 001; Abusaleh M. Jabir; Dhiraj K. Pradhan (VLSI Design, 2008)

On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set. - Hafizur Rahaman 001; Dipak Kumar Kole; Debesh Kumar Das; Bhargab B. Bhattacharya (VLSI Design, 2008)

Derivation of Reduced Test Vectors for Bit-Parallel Multipliers over GF(2^m). - Hafizur Rahaman 001; Jimson Mathew; Dhiraj K. Pradhan; Abusaleh M. Jabir (IEEE Trans. Computers, 2008)

An Adaptive BIST Design for Detecting Multiple Stuck-Open Faults in a CMOS Complex Cell. - Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (IEEE Trans. Instrum. Meas., 2008)

C-testable bit parallel multipliers over GF(2m). - Hafizur Rahaman 001; Jimson Mathew; Dhiraj K. Pradhan; Abusaleh M. Jabir (ACM Trans. Design Autom. Electr. Syst., 2008)

C-testable S-box implementation for secure advanced encryption standard. - Hafizur Rahaman 001; Jimson Mathew; Abusaleh M. Jabir; Dhiraj K. Pradhan (IOLTS, 2009)

A Method for the Multi-Net Multi-Pin Routing Problem with Layer Assignment. - Tuhina Samanta; Hafizur Rahaman 001; Prasun Ghosal; Parthasarathi Dasgupta (VLSI Design, 2009)

Testable design of AND-EXOR logic networks with universal test sets. - Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (Comput. Electr. Eng., 2009)

Single error correctable bit parallel multipliers over GF(2m). - Jimson Mathew; Abusaleh M. Jabir; Hafizur Rahaman 001; Dhiraj K. Pradhan (IET Comput. Digit. Tech., 2009)

Non-preemptive test scheduling for Network-on-Chip(NoC) based systems by reusing NoC as TAM. - Goutam Mali; Suman Das; Hafizur Rahaman 001; Chandan Giri (APCCAS, 2010)

Derivation of Optimal Test Set for Detection of Multiple Missing-Gate Faults in Reversible Circuits. - Dipak Kumar Kole; Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (Asian Test Symposium, 2010)

Testing of Digital Microfluidic Biochips Using Improved Eulerization Techniques and the Chinese Postman Problem. - Debasis Mitra 002; Sarmishtha Ghoshal; Hafizur Rahaman 001; Krishnendu Chakrabarty; Bhargab B. Bhattacharya (Asian Test Symposium, 2010)

Minimizing Thermal Disparities during Placement in 3D ICs. - Prasun Ghosal; Hafizur Rahaman 001; Parthasarathi Dasgupta (CSE, 2010)

Unified Digit Serial Systolic Montgomery Multiplication Architecture for Special Classes of Polynomials over GF(2m). - Somsubhra Talapatra; Hafizur Rahaman 001; Samir K. Saha (DSD, 2010)

A novel droplet routing algorithm for digital microfluidic biochips. - Pranab Roy; Hafizur Rahaman 001; Parthasarathi Dasgupta (ACM Great Lakes Symposium on VLSI, 2010)

On the design of different concurrent EDC schemes for S-Box and GF(p). - Jimson Mathew; Hafizur Rahaman 001; Abusaleh M. Jabir; Saraju P. Mohanty; Dhiraj K. Pradhan (ISQED, 2010)

SSMCA: CA based Segmented Sensor Network Management scheme. - Indrajit Banerjee; Sukanta Das; Hafizur Rahaman 001; Biplab K. Sikdar; Mamata Dalui (SMC, 2010)

On the synthesis of attack tolerant cryptographic hardware. - Jimson Mathew; Savita Banerjee; Hafizur Rahaman 001; Dhiraj K. Pradhan; Saraju P. Mohanty; Abusaleh M. Jabir (VLSI-SoC, 2010)

Low complexity montgomery multiplication architecture for elliptic curve cryptography over GF(pm). - Somsubhra Talapatra; Hafizur Rahaman 001 (VLSI-SoC, 2010)

Secure Testable S-box Architecture for Cryptographic Hardware Implementation. - Hafizur Rahaman 001; Jimson Mathew; Dhiraj K. Pradhan (Comput. J., 2010)

A Galois field-based logic synthesis with testability. - Jimson Mathew; Abusaleh M. Jabir; Ashutosh Kumar Singh 001; Hafizur Rahaman 001; Dhiraj K. Pradhan (IET Comput. Digit. Tech., 2010)

Simplified bit parallel systolic multipliers for special class of galois field (2m) with testability. - Hafizur Rahaman 001; Jimson Mathew; Abusaleh M. Jabir; Dhiraj K. Pradhan (IET Comput. Digit. Tech., 2010)

Test Generation in Systolic Architecture for Multiplication Over GF(2 m). - Hafizur Rahaman 001; Jimson Mathew; Dhiraj K. Pradhan (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Low Complexity Digit Serial Systolic Montgomery Multipliers for Special Class of GF(2m). - Somsubhra Talapatra; Hafizur Rahaman 001; Jimson Mathew (IEEE Trans. Very Large Scale Integr. Syst., 2010)

DFDNM: A Distributed Fault Detection and Node Management Scheme for Wireless Sensor Network. - Indrajit Banerjee; Prasenjit Chanak; Biplab Kumar Sikdar; Hafizur Rahaman 001 (ACC (3), 2011)

Obstacle Aware Routing in 3D Integrated Circuits. - Prasun Ghosal; Hafizur Rahaman 001; Satrajit Das; Arindam Das; Parthasarathi Dasgupta (ADCONS, 2011)

A Multi-pin Droplet Routing Algorithm for Digital Microfluidic Biochips. - Pranab Roy; Hafizur Rahaman 001; Parthasarathi Dasgupta (BIODEVICES, 2011)

On residue removal in digital microfluidic biochips. - Debasis Mitra 002; Sarmishtha Ghoshal; Hafizur Rahaman 001; Krishnendu Chakrabarty; Bhargab B. Bhattacharya (ACM Great Lakes Symposium on VLSI, 2011)

Fast high-performance algorithms for multi-pin droplet routing in digital microfluidic biochips. - Pranab Roy; Hafizur Rahaman 001; Parthasarathi Dasgupta (ACM Great Lakes Symposium on VLSI, 2011)

SBFDR: Sector Based Fault Detection and Recovery in Wireless Sensor Networks. - Indrajit Banerjee; Prasenjit Chanak; Hafizur Rahaman 001 (HPAGC, 2011)

Crosstalk and Gate Oxide Reliability Analysis in Graphene Nanoribbon Interconnects. - Debaprasad Das; Hafizur Rahaman 001 (ISED, 2011)

Runtime Congestion and Crosstalk Aware Router for FPGA Using Jbits3.0 for Partial Reconfigurable Application. - Nachiketa Das; Pranab Roy; Hafizur Rahaman 001 (ISED, 2011)

Derivation of Automatic Test Set for Detection of Missing Gate Faults in Reversible Circuits. - Dipak Kumar Kole; Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (ISED, 2011)

Ant Colony Optimization Based Droplet Routing Technique in Digital Microfluidic Biochip. - Indrajit Pan; Parthasarathi Dasgupta; Hafizur Rahaman 001; Tuhina Samanta (ISED, 2011)

Optimizing Test Architecture for TSV Based 3D Stacked ICs Using Hard SOCs. - Surajit Kumar Roy; Chandan Giri; Arnab Chakraborty; Subhro Mukherjee; Debesh K. Das; Hafizur Rahaman 001 (ISED, 2011)

Optimization of Test Wrapper for TSV Based 3D SOCs. - Surajit Kumar Roy; Chandan Giri; Sourav Ghosh; Hafizur Rahaman 001 (ISED, 2011)

A Best Path Selection Based Parallel Router for DMFBs. - Pranab Roy; Hafizur Rahaman 001; Rupam Bhattacharya; Parthasarathi Dasgupta (ISED, 2011)

Crosstalk aware coupled line delay tree construction for on-chip interconnects. - Tuhina Samanta; Sanoara Khatun; Hafizur Rahaman 001; Parthasarathi Dasgupta (ISQED, 2011)

Optimizing Test Wrapper for Embedded Cores Using TSV Based 3D SOCs. - Surajit Kumar Roy; Chandan Giri; Sourav Ghosh; Hafizur Rahaman 001 (ISVLSI, 2011)

A Group-Preferential Parallel-Routing Algorithm for Cross-Referencing Digital Microfluidic Biochips. - Pranab Roy; Rajesh Mandal; Hafizur Rahaman 001; Parthasarathi Dasgupta (ISVLSI, 2011)

DJSS: Distributed job scheduling scheme for WSN. - Indrajit Banerjee; Prasenjit Chanak; Anirban Datta; Hafizur Rahaman 001 (ReTIS, 2011)

Fault diagnosis in reversible circuits under missing-gate fault model. - Hafizur Rahaman 001; Dipak Kumar Kole; Debesh K. Das; Bhargab B. Bhattacharya (Comput. Electr. Eng., 2011)

CCABC: Cyclic Cellular Automata Based Clustering For Energy Conservation in Sensor Networks - Indrajit Banerjee; Prasenjit Chanak; Hafizur Rahaman 001 (CoRR, 2011)

Pseudo-Parallel Datapath Structure for Power Optimal Implementation of 128-pt FFT/IFFT for WPAN. - Jimson Mathew; Koushik Maharatna; Babita R. Jose; Hafizur Rahaman 001; Dhiraj K. Pradhan (Circuits Syst. Signal Process., 2011)

Test Planning in Digital Microfluidic Biochips Using Efficient Eulerization Techniques. - Debasis Mitra 002; Sarmishtha Ghoshal; Hafizur Rahaman 001; Krishnendu Chakrabarty; Bhargab B. Bhattacharya (J. Electron. Test., 2011)

Near-optimal Y-routed delay trees in nanometric interconnect design. - Tuhina Samanta; Hafizur Rahaman 001; Parthasarathi Dasgupta (IET Comput. Digit. Tech., 2011)

On-Line Error Detection in Digital Microfluidic Biochips. - Debasis Mitra 002; Sarmishtha Ghoshal; Hafizur Rahaman 001; Krishnendu Chakrabarty; Bhargab B. Bhattacharya (Asian Test Symposium, 2012)

A New Look Ahead Technique for Customized Testing in Digital Microfluidic Biochips. - Pranab Roy; Hafizur Rahaman 001; Parthasarathi Dasgupta; Bhargab B. Bhattacharya (Asian Test Symposium, 2012)

Automated path planning for washing in digital microfluidic biochips. - Debasis Mitra 002; Sarmishtha Ghoshal; Hafizur Rahaman 001; Krishnendu Chakrabarty; Bhargab B. Bhattacharya (CASE, 2012)

An intelligent compaction technique for pin constrained routing in cross referencing digital microfluidic biochips. - Pranab Roy; Rupam Bhattacharjee; Modud Sohid; Sudipta Chakraborty; Hafizur Rahaman 001; Parthasarathi Dasgupta (CODES+ISSS, 2012)

Diametric Mesh of Tree (DiaMoT) Routing Framework for High Performance NoCs: A Hierarchical Approach. - Prasun Ghosal; Sunita Choudhuri; Hafizur Rahaman 001 (HPCC-ICESS, 2012)

Design of 4-Bit Array Multiplier Using Multi-wall Carbon Nanotube Interconnects. - Debaprasad Das; Sourav Das; Hafizur Rahaman 001 (ISED, 2012)

Particle Swarm Optimization Based Circuit Synthesis of Reversible Logic. - Kamalika Datta; Indranil Sengupta 001; Hafizur Rahaman 001 (ISED, 2012)

Reversible Logic Circuit Synthesis Using Genetic Algorithm and Particle Swarm Optimization. - Papia Manna; Dipak Kumar Kole; Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (ISED, 2012)

System on Biochips: A New Design for Integration of Multiple DMFBs. - Pranab Roy; Moudud Sohid; Sudipta Chakraborty; Hafizur Rahaman 001; Parthasarathi Dasgupta (ISED, 2012)

Efficient and Compact Electrical Modeling of Multi Walled Carbon Nanotube Interconnects. - Manodipan Sahoo; Prasun Ghosal; Hafizur Rahaman 001 (ISED, 2012)

Binary Difference Based Test Data Compression for NoC Based SoCs. - Sanga Chaki; Chandan Giri; Hafizur Rahaman 001 (ISVLSI, 2012)

A New Algorithm for Routing-Aware Net Placement in Cross-Referencing Digital Microfluidic Biochips. - Pranab Roy; Rupam Bhattacharjee; Hafizur Rahaman 001; Parthasarathi Dasgupta (ISVLSI, 2012)

A new digital analyzer for optically detected samples in Digital Microfluidic Biochips. - Pranab Roy; Sudipta Chakraborty; Moudud Sohid; Hafizur Rahaman 001; Parthasarathi Dasgupta (MWSCAS, 2012)

Partitioning-based wirelength estimation technique for Y-routing. - Tuhina Samanta; Hafizur Rahaman 001; Parthasarathi Dasgupta (SBCCI, 2012)

A heuristic method for obstacle avoiding group Steiner tree construction. - Tuhina Samanta; Raka Sardar; Hafizur Rahaman 001; Parthasarathi Dasgupta; Bhargab B. Bhattacharya (SLIP, 2012)

Design of an NoC with on-chip photonic interconnects using adaptive CDMA links. - Soumyajit Poddar; Prasun Ghosal; Priyajit Mukherjee; Suman Samui; Hafizur Rahaman 001 (SoCC, 2012)

Delay Uncertainty in Single- and Multi-Wall Carbon Nanotube Interconnects. - Debaprasad Das; Hafizur Rahaman 001 (VDAT, 2012)

Design of Content Addressable Memory Architecture Using Carbon Nanotube Field Effect Transistors. - Debaprasad Das; Avishek Sinha Roy; Hafizur Rahaman 001 (VDAT, 2012)

VLSI Architecture for Spatial Domain Spread Spectrum Image Watermarking Using Gray-Scale Watermark. - Sudip Ghosh 001; Somsubhra Talapatra; Debasish Mondal; Navonil Chatterjee; Hafizur Rahaman 001; Santi P. Maity (VDAT, 2012)

Simulation Study of an Ultra Thin Body Silicon On Insulator Tunnel Field Effect Transistor. - Partha Sarathi Gupta; Sayan Kanungo; Hafizur Rahaman 001; Parthasarathi Dasgupta (VDAT, 2012)

A Photonic Network on Chip with CDMA Links. - Soumyajit Poddar; Prasun Ghosal; Priyajit Mukherjee; Suman Samui; Hafizur Rahaman 001 (VDAT, 2012)

VLSI Architecture for Bit Parallel Systolic Multipliers for Special Class of GF(2 m )Using Dual Bases. - Hafizur Rahaman 001; Jimson Mathew; Abusaleh M. Jabir; Dhiraj K. Pradhan (VDAT, 2012)

Post-bond Stack Testing for 3D Stacked IC. - Surajit Kumar Roy; Dona Roy; Chandan Giri; Hafizur Rahaman 001 (VDAT, 2012)

Synthesis of Reversible Circuits Using Heuristic Search Method. - Kamalika Datta; Gaurav Rathi; Indranil Sengupta 001; Hafizur Rahaman 001 (VLSI Design, 2012)

A Heuristic Method for Co-optimization of Pin Assignment and Droplet Routing in Digital Microfluidic Biochip. - Ritwik Mukherjee; Hafizur Rahaman 001; Indrajit Banerjee; Tuhina Samanta; Parthasarathi Dasgupta (VLSI Design, 2012)

Two-level clustering-based techniques for intelligent droplet routing in digital microfluidic biochips. - Pranab Roy; Hafizur Rahaman 001; Parthasarathi Dasgupta (Integr., 2012)

Optimal stacking of SOCs in a 3D-SIC for post-bond testing. - Manjari Pradhan; Chandan Giri; Hafizur Rahaman 001; Debesh K. Das (3DIC, 2013)

Faulty TSVs identification and recovery in 3D stacked ICs during pre-bond testing. - Surajit Kumar Roy; Sobitri Chatterjee; Chandan Giri; Hafizur Rahaman 001 (3DIC, 2013)

Reversible logic implementation of AES algorithm. - Kamalika Datta; Vishal Shrivastav; Indranil Sengupta 001; Hafizur Rahaman 001 (DTIS, 2013)

A new cross contamination aware routing method with intelligent path exploration in digital microfluidic biochips. - Pranab Roy; Pampa Howladar; Rupam Bhattacharjee; Hafizur Rahaman 001; Parthasarathi Dasgupta (DTIS, 2013)

A design for testability technique for quantum reversible circuits. - Joyati Mondal; Debesh K. Das; Dipak Kumar Kole; Hafizur Rahaman 001 (EWDTS, 2013)

Reversible synthesis of symmetric boolean functions based on unate decomposition. - Arighna Deb; Debesh K. Das; Hafizur Rahaman 001; Bhargab B. Bhattacharya (ACM Great Lakes Symposium on VLSI, 2013)

A new customized testing technique using a novel design of droplet motion detector for digital microfluidic Biochip systems. - Pranab Roy; Hafizur Rahaman 001; Partha Sarathi Gupta; Parthasarathi Dasgupta (ICACCI, 2013)

An evolutionary approach to reversible logic synthesis using output permutation. - Kamalika Datta; Indranil Sengupta 001; Hafizur Rahaman 001; Rolf Drechsler (IDT, 2013)

Optimizing test architecture of 3D stacked ICs for partial stack/complete stack using hard SoCs. - Surajit Kumar Roy; Chandan Giri; Hafizur Rahaman 001 (IDT, 2013)

Novel designs of digital detection analyzer for intelligent detection and analysis in digital microfluidic biochips. - Pranab Roy; Mahua Raha Patra; Hafizur Rahaman 001; Parthasarathi Dasgupta (IDT, 2013)

Power constraints test scheduling of 3D stacked ICs. - Surajit Kumar Roy; Joy Sankar Sengupta; Chandan Giri; Hafizur Rahaman 001 (IDT, 2013)

Digital microfluidic system: A new design for heterogeneous sample based integration of multiple DMFBs. - Pranab Roy; Mahua Raha Patra; Hafizur Rahaman 001; Parthasarathi Dasgupta (ISCAS, 2013)

ESOP-Based Synthesis of Reversible Circuit Using Improved Cube List. - Chandan Bandyopadhyay; Debashri Roy; Dipak Kumar Kole; Kamalika Datta; Hafizur Rahaman 001 (ISED, 2013)

An Area and Power Efficient Dynamic TDMA Based Photonic Network on Chip. - Soumyajit Poddar; Prasun Ghosal; Priyajit Mukherjee; Suman Samui; Hafizur Rahaman 001 (ISED, 2013)

An Intelligent Biochip System for Diagnostic Process Flow Based Integration of Combined Detection Analyzer. - Pranab Roy; Mahua Raha Patra; Hafizur Rahaman 001; Parthasarathi Dasgupta (ISED, 2013)

Impact of Inductance on the Performance of Single Walled Carbon Nanotube Bundle Interconnects. - Manodipan Sahoo; Hafizur Rahaman 001; Bhargab B. Bhattacharya (ISED, 2013)

Multi-objective optimization algorithm for efficient pin-constrained droplet routing technique in digital microfluidic biochip. - Soumyajit Chatterjee; Hafizur Rahaman 001; Tuhina Samanta (ISQED, 2013)

Exploiting Negative Control Lines in the Optimization of Reversible Circuits. - Kamalika Datta; Gaurav Rathi; Robert Wille; Indranil Sengupta 001; Hafizur Rahaman 001; Rolf Drechsler (RC, 2013)

Reversible Circuit Synthesis of Symmetric Functions Using a Simple Regular Structure. - Arighna Deb; Debesh K. Das; Hafizur Rahaman 001; Bhargab B. Bhattacharya; Robert Wille; Rolf Drechsler (RC, 2013)

On Designing Testable Reversible Circuits Using Gate Duplication. - Joyati Mondal; Debesh Kumar Das; Dipak Kumar Kole; Hafizur Rahaman 001; Bhargab B. Bhattacharya (VDAT, 2013)

A New Method for Route Based Synthesis and Placement in Digital Microfluidic Biochips. - Pranab Roy; Samadrita Bhattacharya; Hafizur Rahaman 001; Parthasarathi Dasgupta (VDAT, 2013)

Bridging fault detection in cluster based FPGA by using Muller C element. - Nachiketa Das; Pranab Roy; Hafizur Rahaman 001 (Comput. Electr. Eng., 2013)

Derivation of test set for detecting multiple missing-gate faults in reversible circuits. - Dipak Kumar Kole; Hafizur Rahaman 001; Debesh K. Das; Bhargab B. Bhattacharya (Comput. Electr. Eng., 2013)

Optimization algorithms for the design of digital microfluidic biochips: A survey. - Indrajit Pan; Ritwik Mukherjee; Hafizur Rahaman 001; Tuhina Samanta; Parthasarathi Dasgupta (Comput. Electr. Eng., 2013)

Built-in-self-test technique for diagnosis of delay faults in cluster-based field programmable gate arrays. - Nachiketa Das; Pranab Roy; Hafizur Rahaman 001 (IET Comput. Digit. Tech., 2013)

Particle Swarm Optimization Based Reversible Circuit Synthesis Using Mixed Control Toffoli Gates. - Kamalika Datta; Indranil Sengupta 001; Hafizur Rahaman 001 (J. Low Power Electron., 2013)

An ESOP-Based Reversible Circuit Synthesis Flow Using Simulated Annealing. - Kamalika Datta; Alhaad Gokhale; Indranil Sengupta 001; Hafizur Rahaman 001 (ACSS (2), 2014)

Generator for Test Set Construction of SMGF in Reversible Circuit by Boolean Difference Method. - Bappaditya Mondal; Dipak Kumar Kole; Debesh Kumar Das; Hafizur Rahaman 001 (ATS, 2014)

Digital Design and Pipelined Architecture for Reversible Watermarking Based on Difference Expansion Using FPGA. - Sudip Ghosh 001; Nachiketa Das; Subhajit Das 001; Santi P. Maity; Hafizur Rahaman 001 (ICIT, 2014)

A layout based customized testing technique for total microfluidic operations in digital microfluidic biochips. - Pranab Roy; Hafizur Rahaman 001; Parthasarathi Dasgupta (DDECS, 2014)

Optimizing DD-based synthesis of reversible circuits using negative control lines. - Eleonora Schönborn; Kamalika Datta; Robert Wille; Indranil Sengupta 001; Hafizur Rahaman 001; Rolf Drechsler (DDECS, 2014)

Optimizing test time for core-based 3-d integrated circuits by a technique of bi-partitioning. - Manjari Pradhan; Debesh K. Das; Chandan Giri; Hafizur Rahaman 001 (EWDTS, 2014)

A new technique for layout based functional testing of modules in Digital Microfluidic Biochips. - Pranab Roy; Samadrita Bhattacharya; Hafizur Rahaman 001; Parthasarathi Dasgupta (EWDTS, 2014)

Automated two stage detection and analyzer system in multipartitioned Digital Microfluidic Biochips. - Pranab Roy; Aatreyi Bal; Mahua Raha Patra; Hafizur Rahaman 001; Parthasarathi Dasgupta (ISCAS, 2014)

An ABCD parameter based modeling and analysis of crosstalk induced effects in Multilayer Graphene Nano Ribbon interconnects. - Manodipan Sahoo; Hafizur Rahaman 001 (ISCAS, 2014)

Design of a Low Complexity and Fast Hardware Architecture for Digital Image Watermarking in FWHT Domain on FPGA. - Sudip Ghosh 001; Arijit Biswas; Santi P. Maity; Hafizur Rahaman 001 (ISED, 2014)

A Novel GNR Interconnect Model to Reduce Crosstalk Delay. - Sandip Bhattacharya; Debaprasad Das; Hafizur Rahaman 001 (ISED, 2014)

Diagnosis of SMGF in ESOP Based Reversible Logic Circuit. - Bappaditya Mondal; Chandan Bandyopadhyay; Dipak Kumar Kole; Jimson Mathew; Hafizur Rahaman 001 (ISED, 2014)

Multilevel Homogeneous Detection Analyzer for Medical Diagnostic Application in Digital Microfluidic Biochips. - Pranab Roy; Tamosa Chakraborty; Hafizur Rahaman 001; Parthasarathi Dasgupta (ISED, 2014)

Impact of Line Resistance Variations on Crosstalk Delay and Noise in Multilayer Graphene Nano Ribbon Interconnects. - Manodipan Sahoo; Hafizur Rahaman 001 (ISED, 2014)

A Cube Pairing Approach for Synthesis of ESOP-Based Reversible Circuit. - Chandan Bandyopadhyay; Hafizur Rahaman 001; Rolf Drechsler (ISMVL, 2014)

Mach-Zehnder Interferometer Based All Optical Reversible Carry-Lookahead Adder. - Pratik Dutta; Chandan Bandyopadhyay; Chandan Giri; Hafizur Rahaman 001 (ISVLSI, 2014)

Session Based Core Test Scheduling for 3D SOCs. - Surajit Kumar Roy; Payel Ghosh; Hafizur Rahaman 001; Chandan Giri (ISVLSI, 2014)

A 45 uW 13 pJ/conv-step 7.4-ENOB 40 kS/s SAR ADC for digital microfluidic biochip applications. - Indrajit Das; Manodipan Sahoo; Pranab Roy; Hafizur Rahaman 001 (VDAT, 2014)

All optical implementation of Mach-Zehnder interferometer based reversible sequential circuit. - Pratik Dutta; Chandan Bandyopadhyay; Hafizur Rahaman 001 (VDAT, 2014)

A Novel Wire Planning Technique for Optimum Pin Utilization in Digital Microfluidic Biochips. - Pranab Roy; Samadrita Bhattacharya; Rupam Bhattacharyay; Firdousi Jamil Imam; Hafizur Rahaman 001; Parthasarathi Dasgupta (VLSID, 2014)

An ABCD Parameter Based Modeling and Analysis of Crosstalk Induced Effects in Multiwalled Carbon Nanotube Bundle Interconnects. - Manodipan Sahoo; Prasun Ghosal; Hafizur Rahaman 001 (VLSID, 2014)

Effective fault detection and routing scheme for wireless sensor networks. - Indrajit Banerjee; Prasenjit Chanak; Hafizur Rahaman 001; Tuhina Samanta (Comput. Electr. Eng., 2014)

An Improved Reversible Circuit Synthesis Approach using Clustering of ESOP Cubes. - Kamalika Datta; Gaurav Rathi; Indranil Sengupta 001; Hafizur Rahaman 001 (ACM J. Emerg. Technol. Comput. Syst., 2014)

On the Suitability of Single-Walled Carbon Nanotube Bundle Interconnects for High-Speed and Power-Efficient Applications. - Manodipan Sahoo; Hafizur Rahaman 001; Bhargab B. Bhattacharya (J. Low Power Electron., 2014)

Improved Cube List Based Cube Pairing Approach for Synthesis of ESOP Based Reversible Logic. - Chandan Bandyopadhyay; Hafizur Rahaman 001; Rolf Drechsler (Trans. Comput. Sci., 2014)

An Approach to Reversible Logic Synthesis Using Input and Output Permutations. - Kamalika Datta; Indranil Sengupta 001; Hafizur Rahaman 001; Rolf Drechsler (Trans. Comput. Sci., 2014)

Boolean Difference Technique for Detecting All Missing Gate Faults in Reversible Circuits. - Joyati Mondal; Bappaditya Mondal; Dipak Kumar Kole; Hafizur Rahaman 001; Debesh K. Das (DDECS, 2015)

3D integration in biochips: New proposed architectures for 3D applications in ATDA based digital microfluidic biochips. - Pranab Roy; Pampa Howladar; Raja Dastidar; Hafizur Rahaman 001; Parthasarathi Dasgupta (DTIS, 2015)

Recovery of faulty TSVs in 3D ICs. - Surajit Kumar Roy; Kaustav Roy; Chandan Giri; Hafizur Rahaman 001 (ISQED, 2015)

An adaptive feedback based reversible watermarking algorithm using difference expansion. - Sudip Ghosh 001; Nachiketa Das; Subhajit Das 001; Santi Prasad Maity; Hafizur Rahaman 001 (ReTIS, 2015)

Adaptive CDMA based multicast method for photonic networks on chip. - Soumyajit Poddar; Prasun Ghosal; Hafizur Rahaman 001 (SoCC, 2015)

Improved supply regulation and temperature compensated current reference circuit with low process variations. - Suraj Gupta; Sabir Ali Mondal; Hafizur Rahaman 001 (VDAT, 2015)

A thermal estimation model for 3D IC using liquid cooled microchannels and thermal TSVs. - Surajit Kumar Roy; Supriyo Mandal; Chandan Giri; Hafizur Rahaman 001 (VLSI-SoC, 2015)

All Optical Implementation of Mach-Zehnder Interferometer Based Reversible Sequential Counters. - Pratik Dutta; Chandan Bandyopadhyay; Hafizur Rahaman 001 (VLSID, 2015)

BDD-Based Synthesis for All-Optical Mach-Zehnder Interferometer Circuits. - Eleonora Schönborn; Kamalika Datta; Robert Wille; Indranil Sengupta 001; Hafizur Rahaman 001; Rolf Drechsler (VLSID, 2015)

Load management scheme for energy holes reduction in wireless sensor networks. - Prasenjit Chanak; Indrajit Banerjee; Hafizur Rahaman 001 (Comput. Electr. Eng., 2015)

Optimisation of test architecture in three-dimensional stacked integrated circuits for partial stack/complete stack using hard system-on-chips. - Surajit Kumar Roy; Chandan Giri; Hafizur Rahaman 001 (IET Comput. Digit. Tech., 2015)

Modeling of Crosstalk Induced Effects in Copper-Based Nanointerconnects: An ABCD Parameter Matrix-Based Approach. - Manodipan Sahoo; Hafizur Rahaman 001 (J. Circuits Syst. Comput., 2015)

Field Programmable Gate Array and System-on-Chip Based Implementation of Discrete Fast Walsh-Hadamard Transform Domain Image Watermarking Architecture for Real-Time Applications. - Sudip Ghosh 001; Arijit Biswas; Santi Prasad Maity; Hafizur Rahaman 001 (J. Low Power Electron., 2015)

Selected Articles from the IEEE ISED 2014 Conference. - Jimson Mathew; Hafizur Rahaman 001; Priyadarsan Patra; Dhiraj K. Pradhan (J. Low Power Electron., 2015)

A Post-Synthesis Optimization Technique for Reversible Circuits Exploiting Negative Control Lines. - Kamalika Datta; Indranil Sengupta 001; Hafizur Rahaman 001 (IEEE Trans. Computers, 2015)

Offline Washing Schemes for Residue Removal in Digital Microfluidic Biochips. - Debasis Mitra 002; Sarmishtha Ghoshal; Hafizur Rahaman 001; Krishnendu Chakrabarty; Bhargab B. Bhattacharya (ACM Trans. Design Autom. Electr. Syst., 2015)

TSV-aware 3-D IC structural planning with irregular die-size. - Arko Dutt; Pranab Roy; Hafizur Rahaman 001 (APCCAS, 2016)

Parametric Fault Detection in Analog Circuits: A Statistical Approach. - Supriyo Srimani; Kasturi Ghosh; Hafizur Rahaman 001 (ATS, 2016)

A synthesis approach for ESOP-based reversible circuit. - Chandan Bandyopadhyay; Shalini Parekh; Hafizur Rahaman 001 (ICACCI, 2016)

Design of memristor-based up-down counter using material implication logic. - Anindita Chakraborty; Aparna Dhara; Hafizur Rahaman 001 (ICACCI, 2016)

An automated design of pin-constrained digital microfluidic biochip on MEDA architecture. - Pampa Howladar; Pranab Roy; Hafizur Rahaman 001 (ICACCI, 2016)

Cross-reference EWOD driving scheme and cross-contamination aware net placement technique for MEDA based DMFBs. - Pampa Howladar; Debashri Roy; Pranab Roy; Hafizur Rahaman 001 (ICACCI, 2016)

High-speed decoder design using memristor-based nano-crossbar architecture. - Malay Kule; Avik Dutta; Hafizur Rahaman 001; Bhargab B. Bhattacharya (ISED, 2016)

A testing scheme for mixed-control based reversible circuits. - Bappaditya Mondal; Chandan Bandyopadhyay; Hafizur Rahaman 001 (ISED, 2016)

VLSI thermal placement issues: A cooperative game theory based approach. - Arindam Sinharay; Pranab Roy; Hafizur Rahaman 001 (ISED, 2016)

Nearest-Neighbor and Fault-Tolerant Quantum Circuit Implementation. - Laxmidhar Biswal; Chandan Bandyopadhyay; Anupam Chattopadhyay; Robert Wille; Rolf Drechsler; Hafizur Rahaman 001 (ISMVL, 2016)

Temperature dependent IR-drop and delay analysis in side-contact multilayer graphene nanoribbon based power interconnects. - Sandip Bhattacharya; Debaprasad Das; Hafizur Rahaman 001 (VDAT, 2016)

BDD based synthesis technique for design of high-speed memristor based circuits. - Anindita Chakraborty; Rakesh Das; Chandan Bandyopadhyay; Hafizur Rahaman 001 (VDAT, 2016)

Synthesis aware sample preparation techniques using random sample sets in DMFB. - Pranab Roy; Sudeshna Chakraborty; Hafizur Rahaman 001 (VDAT, 2016)

Improving the Realization of Multiple-Control Toffoli Gates Using the NCVW Quantum Gate Library. - Laxmidhar Biswal; Chandan Bandyopadhyay; Robert Wille; Rolf Drechsler; Hafizur Rahaman 001 (VLSID, 2016)

Optimization of Test Wrapper for TSV Based 3D SOCs. - Surajit Kumar Roy; Chandan Giri; Hafizur Rahaman 001 (J. Electron. Test., 2016)

Investigating the Applicability of Graphene Nanoribbon as Signal and Power Interconnects for Nanometer Designs. - Debaprasad Das; Hafizur Rahaman 001 (J. Circuits Syst. Comput., 2016)

Reversible Synthesis of Symmetric Functions with a Simple Regular Structure and Easy Testability. - Arighna Deb; Debesh K. Das; Hafizur Rahaman 001; Robert Wille; Rolf Drechsler; Bhargab B. Bhattacharya (ACM J. Emerg. Technol. Comput. Syst., 2016)

Modeling and analysis of crosstalk induced overshoot/undershoot effects in multilayer graphene nanoribbon interconnects and its impact on gate oxide reliability. - Manodipan Sahoo; Hafizur Rahaman 001 (Microelectron. Reliab., 2016)

Design of a High-Performance CDMA-Based Broadcast-Free Photonic Multi-Core Network on Chip. - Soumyajit Poddar; Prasun Ghosal; Hafizur Rahaman 001 (ACM Trans. Embed. Comput. Syst., 2016)

Novel Wire Planning Schemes for Pin Minimization in Digital Microfluidic Biochips. - Pranab Roy; Swati Saha; Hafizur Rahaman 001; Parthasarathi Dasgupta (IEEE Trans. Very Large Scale Integr. Syst., 2016)

TSV repairing for 3D ICs using redundant TSV. - Sudeep Ghosh; Surajit Kumar Roy; Hafizur Rahaman 001; Chandan Giri (ISED, 2017)

All optical design of cost efficient multiplier circuit using terahertz optical asymmetric demultiplexer. - Arpan Manna; Subham Saha; Rakesh Das; Chandan Bandyopadhyay; Hafizur Rahaman 001 (ISED, 2017)

Detection and localization of appearance faults in reversible circuits. - Bappaditya Mondal; Chandan Bandyopadhyay; Hafizur Rahaman 001 (ISED, 2017)

OTORNoC: Optical tree of rings network on chip for 1000 core systems. - Soumyajit Poddar; Suraj; Amit Kumar Yadav; Hafizur Rahaman 001 (ISED, 2017)

Adaptive medical detection system: An iterative averaging method for automated detection analysis using DMFBs. - Pranab Roy; Amiya Sahoo; Hafizur Rahaman 001 (ISED, 2017)

Modeling and Analysis of Transient Heat for 3D IC. - Subhajit Chatterjee; Surajit Kumar Roy; Chandan Giri; Hafizur Rahaman 001 (VDAT, 2017)

Improving the Design of Nearest Neighbor Quantum Circuits in 2D Space. - Neha Chaudhuri; Chandan Bandyopadhyay; Hafizur Rahaman 001 (VDAT, 2017)

Hausdorff Distance Driven L-Shape Matching Based Layout Decomposition for E-Beam Lithography. - Arindam Sinharay; Pranab Roy; Hafizur Rahaman 001 (VDAT, 2017)

Analysis of Crosstalk-Induced Effects in Multilayer Graphene Nanoribbon Interconnects. - Manodipan Sahoo; Hafizur Rahaman 001 (J. Circuits Syst. Comput., 2017)

Selected Articles from the IEEE ISED 2016 Conference. - Jimson Mathew; Hafizur Rahaman 001; Priyadarsan Patra; Dhiraj K. Pradhan (J. Low Power Electron., 2017)

Test Diagnosis of Digital Microfluidic Biochips Using Image Segmentation. - Sourav Ghosh; Hafizur Rahaman 001; Chandan Giri (ATS, 2018)

Identification of Faulty TSV with a Built-In Self-Test Mechanism. - Dilip Kumar Maity; Surajit Kumar Roy; Chandan Giri; Hafizur Rahaman 001 (ATS, 2018)

A Novel Approach for Nearest Neighbor Realization of 2D Quantum Circuits. - Anirban Bhattacharjee; Chandan Bandyopadhyay; Robert Wille; Rolf Drechsler; Hafizur Rahaman 001 (ISVLSI, 2018)

A Heuristic Qubit Placement Strategy for Nearest Neighbor Realization in 2D Architecture. - Anirban Bhattacharjee; Chandan Bandyopadhyay; Laxmidhar Biswal; Hafizur Rahaman 001 (VDAT, 2018)

Quantum Domain Design of Clifford+T-Based Bidirectional Barrel Shifter. - Laxmidhar Biswal; Anirban Bhattacharjee; Rakesh Das; Gopinath Thirunavukarasu; Hafizur Rahaman 001 (VDAT, 2018)

An Angular Steiner Tree Based Global Routing Algorithm for Graphene Nanoribbon Circuit. - Arindam Sinharay; Subrata Das; Pranab Roy; Hafizur Rahaman 001 (VDAT, 2018)

Optimized Concurrent Testing of Digital Microfluidic Biochips. - Sourav Ghosh; Hafizur Rahaman 001; Chandan Giri (VLSID, 2018)

Computing Fréchet Distance Metric Based L-Shape Tile Decomposition for E-Beam Lithography. - Arindam Sinharay; Pranab Roy; Hafizur Rahaman 001 (VLSID, 2018)

Correction to: VLSI-Based Pipeline Architecture for Reversible Image Watermarking by Difference Expansion with High-Level Synthesis Approach. - Subhajit Das 001; Sudip Ghosh 001; Nachiketa Das; Santi P. Maity; Hafizur Rahaman 001; Reshmi Maity; Niladri Maity (Circuits Syst. Signal Process., 2018)

Improved circuit synthesis approach for exclusive-sum-of-product-based reversible circuits. - Chandan Bandyopadhyay; Shalini Parekh; Hafizur Rahaman 001 (IET Comput. Digit. Tech., 2018)

Homogeneous droplet routing in DMFB: An enhanced technique for high performance bioassay implementation. - Rupam Bhattacharya; Pranab Roy; Hafizur Rahaman 001 (Integr., 2018)

Analysis of Simultaneous Switching Noise and IR-Drop in Side-Contact Multilayer Graphene Nanoribbon Power Distribution Network. - Sandip Bhattacharya; Debaprasad Das; Hafizur Rahaman 001 (J. Circuits Syst. Comput., 2018)

FPGA implementation of semi-fragile reversible watermarking by histogram bin shifting in real time. - Sambaran Hazra; Sudip Ghosh 001; Sayandip De; Hafizur Rahaman 001 (J. Real Time Image Process., 2018)

Synthesis of circuits based on all-optical Mach-Zehnder Interferometers using Binary Decision Diagrams. - Chandan Bandyopadhyay; Rakesh Das; Robert Wille; Rolf Drechsler; Hafizur Rahaman 001 (Microelectron. J., 2018)

A template-based technique for efficient Clifford+T-based quantum circuit implementation. - Laxmidhar Biswal; Rakesh Das; Chandan Bandyopadhyay; Anupam Chattopadhyay; Hafizur Rahaman 001 (Microelectron. J., 2018)

Effect of Volumetric Split-Errors on Reactant-Concentration During Sample Preparation with Microfluidic Biochips. - Sudip Poddar; Robert Wille; Hafizur Rahaman 001; Bhargab B. Bhattacharya (ACSS (2), 2019)

A low power driver amplifier for Fully Differential ADC. - Sagnik Bhar; Annapurna Mondal; Supriyo Srimani; Indranil Hatai; Subhajit Das 001; Kasturi Ghosh; Hafizur Rahaman 001 (ISDCS, 2019)

Estimation of non-linear effects for Capacitive DAC in SAR ADC: An Analytical Model. - Ajay Kumar Chowdhary; Supriyo Srimani; Subhajit Das 001; Kasturi Ghosh; Hafizur Rahaman 001 (ISDCS, 2019)

Comparative Stability Analysis of Pristine and AsF5 Intercalation Doped Top Contact Graphene Nano Ribbon Interconnects. - Subhajit Das 001; Sandip Bhattacharya; Debaprasad Das; Hafizur Rahaman 001 (ISDCS, 2019)

Optimization of DC-DC Power Converter Design with Second Generation HiSIM_HV Model. - Soumajit Ghosh; Vishal Roshan; Avishek Dutta; Subhajit Das 001; Tapas Kumar Maiti; Mitiko Miura-Mattausch; Hafizur Rahaman 001 (ISDCS, 2019)

Hardware Efficient Convolution Processing Unit for Deep Neural Networks. - Anakhi Hazarika; Soumyajit Poddar; Hafizur Rahaman 001 (ISDCS, 2019)

Fault-tolerant Quantum Implementation of 1-bit and 4-bit Comparator Circuit using Clifford+T-group. - Laxmidhar Biswal; Chandan Bandyopadhyay; Hafizur Rahaman 001 (ISED, 2019)

Efficient Implementation of Fault-Tolerant 4: 1 Quantum Multiplexer (QMUX) Using Clifford+T-Group. - Laxmidhar Biswal; Chandan Bandyopadhyay; Hafizur Rahaman 001 (iSES, 2019)

Distortion Analysis Using Volterra Kernel for Amplifier Circuits. - Supriyo Srimani; Ravi Singh; Manas Kumar Parai; Kasturi Ghosh; Hafizur Rahaman 001 (iSES, 2019)

Micro-electrode-dot Array Based Biochips : Advantages of Using Different Shaped CMAs. - Pampa Howladar; Pranab Roy; Hafizur Rahaman 001 (ISVLSI, 2019)

Shift and Accumulate Convolution Processing Unit. - Anakhi Hazarika; Avinash Jain; Soumyajit Poddar; Hafizur Rahaman 001 (TENCON, 2019)

An Approach for Detection of Node Displacement Fault (NDF) in Reversible Circuit. - Bappaditya Mondal; Anirban Bhattacharjee; Subham Saha; Shalini Parekh; Chandan Bandyopadhyay; Hafizur Rahaman 001 (VDAT, 2019)

Improved Look-Ahead Approaches for Nearest Neighbor Synthesis of 1D Quantum Circuits. - Anirban Bhattacharjee; Chandan Bandyopadhyay; Robert Wille; Rolf Drechsler; Hafizur Rahaman 001 (VLSID, 2019)

Optimizing Quantum Circuits for Modular Exponentiation. - Rakesh Das; Anupam Chattopadhyay; Hafizur Rahaman 001 (VLSID, 2019)

Dilution with Digital Microfluidic Biochips: How Unbalanced Splits Corrupt Target-Concentration. - Sudip Poddar; Robert Wille; Hafizur Rahaman 001; Bhargab B. Bhattacharya (CoRR, 2019)

New techniques for fault-tolerant decomposition of Multi-Controlled Toffoli gate. - Laxmidhar Biswal; Debjyoti Bhattacharjee; Anupam Chattopadhyay; Hafizur Rahaman 001 (CoRR, 2019)

Prevention of Highly Power-Efficient Circuits due to Short-Channel Effects in MOSFETs. - Arnab Mukhopadhyay; Tapas Kumar Maiti; Sandip Bhattacharya; Takahiro Iizuka; Hideyuki Kikuchihara; Mitiko Miura-Mattausch; Hafizur Rahaman 001; Sadayuki Yoshitomi; Dondee Navarro; Hans Jürgen Mattausch (IEICE Trans. Electron., 2019)

Boltzmann transport equation-based semi-classical drain current model for bilayer GFET including scattering effects. - Sudipta Bardhan; Manodipan Sahoo; Hafizur Rahaman 001 (IET Circuits Devices Syst., 2019)

Design and synthesis of improved reversible circuits using AIG- and MIG-based graph data structures. - Chandan Bandyopadhyay; Rakesh Das; Anupam Chattopadhyay; Hafizur Rahaman 001 (IET Comput. Digit. Tech., 2019)

Approach of genetic algorithm for power-aware testing of 3D IC. - Tanusree Kaibartta; Chandan Giri; Hafizur Rahaman 001; Debesh Kumar Das (IET Comput. Digit. Tech., 2019)

A Complete Routing Simulator for Digital Microfluidic Biochip. - Rupam Bhattacharya; Pranab Roy; Hafizur Rahaman 001 (Int. J. Inf. Syst. Model. Des., 2019)

In-memory designing of Delay and Toggle flip-flops utilizing Memristor Aided loGIC (MAGIC). - Anindita Chakraborty; Vivek Saurabh; Partha Sarathi Gupta; Rituraj Kumar; Saikat Majumdar; Smriti Das; Hafizur Rahaman 001 (Integr., 2019)

Fast locking, startup-circuit free, low area, 32-phase analog DLL. - Sabir Ali Mondal; Pradip Mandal; Hafizur Rahaman 001 (Integr., 2019)

A Surface Potential-Based Model for Dual Gate Bilayer Graphene Field Effect Transistor Including the Capacitive Effects. - Sudipta Bardhan; Manodipan Sahoo; Hafizur Rahaman 001 (J. Circuits Syst. Comput., 2019)

Maximal Defect-Free Component in Nanoscale Crossbar Circuits Amidst Stuck-Open and Stuck-Closed Faults. - Malay Kule; Hafizur Rahaman 001; Bhargab B. Bhattacharya (J. Circuits Syst. Comput., 2019)

Boolean Difference Technique for Detecting All Missing Gate and Stuck-at Faults in Reversible Circuits. - Joyati Mondal; Bappaditya Mondal; Dipak Kumar Kole; Hafizur Rahaman 001; Debesh Kumar Das (J. Circuits Syst. Comput., 2019)

A High-performance Homogeneous Droplet Routing Technique for MEDA-based Biochips. - Pampa Howladar; Pranab Roy; Hafizur Rahaman 001 (ACM J. Emerg. Technol. Comput. Syst., 2019)

Error-Oblivious Sample Preparation With Digital Microfluidic Lab-on-Chip. - Sudip Poddar; Robert Wille; Hafizur Rahaman 001; Bhargab B. Bhattacharya (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Potentiality of Data Fusion in Analog Circuit Fault Diagnosis. - Manas Kumar Parai; Kasturi Ghosh; Hafizur Rahaman 001 (ATS, 2020)

Modeling and Analysis of 3D IC Structures for Heat Mitigation by Thermal Through Silicon Vias. - Debika Chaudhuri; Dalia Nandi Das; Hafizur Rahaman 001; Tamal Ghosh (ICIIS, 2020)

Image Classification Based on Approximate Wavelet Transform and Transfer Learning on Deep Convolutional Neural Networks. - Moumita Acharya; Soumyajit Poddar; Amlan Chakrabarti; Hafizur Rahaman 001 (ISDCS, 2020)

Fault-tolerant Quantum Implementation of Priority Encoder Circuit using Clifford+T-group. - Laxmidhar Biswal; Khokan Mondal; Anirban Bhattacharjee; Hafizur Rahaman 001 (ISDCS, 2020)

An Efficient Test Scheduling to Co-optimize Test Time and Peak Power for 3D ICs. - Subhajit Chatterjee; Surajit Kumar Roy; Chandan Giri; Hafizur Rahaman 001 (ISDCS, 2020)

Heat Mitigation in 3D ICs by Improvised TTSV Structure. - Debika Chaudhuri; Dalia Nandi Das; Hafizur Rahaman 001; Tamal Ghosh (ISDCS, 2020)

A Short Review on Graphene Nanoribbon Interconnect. - Subhajit Das 001; Sandip Bhattacharya; Debaprasad Das; Hafizur Rahaman 001 (ISDCS, 2020)

History Effect on Circuit Performance of SOI-MOSFETs. - Soumajit Ghosh; Mitiko Miura-Mattausch; Takahiro Iizuka; Hideyuki Kikuchihara; Hafizur Rahaman 001; Hans Jürgen Mattausch (ISDCS, 2020)

Design of a low power, high speed self calibrated dynamic latched comparator. - Sumit Kumar Jaiswal; Annapurna Mondal; Supriyo Srimani; Subhajit Das 001; Kasturi Ghosh; Hafizur Rahaman 001 (ISDCS, 2020)

An Accelerated Prototype with Movidius Neural Compute Stick for Real-Time Object Detection. - S. P. Kaarmukilan; Anakhi Hazarika; Amal Thomas K.; Soumyajit Poddar; Hafizur Rahaman 001 (ISDCS, 2020)

DFT Based Simulation for Predicting Alcohol Adsorption on Oxygenated Functional Group Containing GO and rGO Based Gas Sensor Devices. - Indranil Maity; Hafizur Rahaman 001; Partha Bhattacharyya (ISDCS, 2020)

A New Blind Invisible and Semi-Fragile Colour Image Watermarking Scheme in Spatial Domain. - Joshua Roy Palathinkal; Yuvam Bhateja; Sudip Ghosh 001; Hafizur Rahaman 001 (ISDCS, 2020)

Microfluidic Cyberphysical Diagnostic System: An ANN Based Application. - Pranab Roy; Amiya Sahoo; Mriganka Chakrabarty; Hafizur Rahaman 001 (ISDCS, 2020)

Valley Resolved Current Components Analysis of Monolayer TMDFETs. - Uttam Kumar Sahu; Ajoy Kumar Saha; Partha Sarathi Gupta; Hafizur Rahaman 001 (ISDCS, 2020)

A New Digital Color Image Watermarking Algorithm with its FPGA and ASIC Implementation. - Shivdeep; Sudip Ghosh 001; Hafizur Rahaman 001 (ISDCS, 2020)

Symmetric Function Based Memristive Polimino PUF with Enhanced Security. - Subhashree Basu; Malay Kule; Hafizur Rahaman 001 (iSES, 2020)

Efficient Implementation of Nearest Neighbor Quantum Circuits Using Clustering with Genetic Algorithm. - Anirban Bhattacharjee; Chandan Bandyopadhyay; Angshu Mukherjee; Robert Wille; Rolf Drechsler; Hafizur Rahaman 001 (ISMVL, 2020)

Post Synthesis-Optimization of Reversible Circuit using Template Matching. - Chandan Bandyopadhyay; Robert Wille; Rolf Drechsler; Hafizur Rahaman 001 (VDAT, 2020)

Analog Circuit Fault Detection by Impulse Response-Based Signature Analysis. - Manas Kumar Parai; Supriyo Srimani; Kasturi Ghosh; Hafizur Rahaman 001 (Circuits Syst. Signal Process., 2020)

Survey on memory management techniques in heterogeneous computing systems. - Anakhi Hazarika; Soumyajit Poddar; Hafizur Rahaman 001 (IET Comput. Digit. Tech., 2020)

Linear Nearest Neighbor Realization of Quantum Circuits Using Clustering and Look-ahead Policy. - Anirban Bhattacharjee; Chandan Bandyopadhyay; Bappaditya Mondal; Hafizur Rahaman 001 (J. Circuits Syst. Comput., 2020)

Detection of Hardware Trojan in Presence of Sneak Path in Memristive Nanocrossbar Circuits. - Subhashree Basu; Malay Kule; Hafizur Rahaman 001 (ISDCS, 2021)

Design of Two-Stage Fully-Differential Driver in SAR ADC with Indirect Feedback Compensation Technique. - Urbashi Basumata; Annapurna Mondal; Subhajit Das 001; Hafizur Rahaman 001 (ISDCS, 2021)

PUF Based Hardware Security: A Review. - Koustav Dey; Malay Kule; Hafizur Rahaman 001 (ISDCS, 2021)

Modelling, Analysis and Optimization of a 4th Order Delta-Sigma ADC and its Non-Idealities for Audio Codec Applications Achieving Dynamic Range Above 100dB. - Bramh Dev Singh; Sourav Naskar; Subhajit Das 001; Hafizur Rahaman 001 (ISDCS, 2021)

A Brief Review of Recent Studies on Performance Improvement of Graphene Nanoribbon Interconnect. - Santasri Giri Tunga; Subhajit Das 001; Hafizur Rahaman 001 (ISDCS, 2021)

An Efficient 2D Mapping of Quantum Circuits to Nearest Neighbor Designs. - Anirban Bhattacharjee; Hafizur Rahaman 001 (iSES, 2021)

Neural Network based Indirect Estimation of Functional Parameters of Amplifier by extracting features from Wavelet Transform. - Supriyo Srimani; Kasturi Ghosh; Hafizur Rahaman 001 (VLSID, 2021)

Simulation-Based Power-Loss Optimization of General-Purpose High-Voltage SiC MOSFET Circuit Under High-Frequency Operation. - Abhishek Kar; Mitiko Miura-Mattausch; Mainak Sengupta; Dondee Navarro; Hideyuki Kikuchihara; Takahiro Iizuka; Hafizur Rahaman 001; Hans Jürgen Mattausch (IEEE Access, 2021)

A Statistical Approach of Analog Circuit Fault Detection Utilizing Kolmogorov-Smirnov Test Method. - Supriyo Srimani; Manas Parai; Kasturi Ghosh; Hafizur Rahaman 001 (Circuits Syst. Signal Process., 2021)

Fault-tolerant quantum implementation of conventional decoder logic with enable input. - Laxmidhar Biswal; Bappaditya Mondal; Hafizur Rahaman 001 (IET Circuits Devices Syst., 2021)

Binary decision diagram-based synthesis technique for improved mapping of Boolean functions inside memristive crossbar-slices. - Anindita Chakraborty; Vivek Maurya; Sneha Prasad; Suryansh Gupta; Rajat Subhra Chakraborty; Hafizur Rahaman 001 (IET Comput. Digit. Tech., 2021)

An ant colony based mapping of quantum circuits to nearest neighbor architectures. - Anirban Bhattacharjee; Chandan Bandyopadhyay; Angshu Mukherjee; Robert Wille; Rolf Drechsler; Hafizur Rahaman 001 (Integr., 2021)

An improved heuristic technique for nearest neighbor realization of quantum circuits in 2D architecture. - Anirban Bhattacharjee; Chandan Bandyopadhyay; Philipp Niemann 001; Bappaditya Mondal; Rolf Drechsler; Hafizur Rahaman 001 (Integr., 2021)

BDD-based synthesis approach for in-memory logic realization utilizing Memristor Aided loGIC (MAGIC). - Anindita Chakraborty; Partha Sarathi Gupta; Ritika Singh; Rakesh Das; Hafizur Rahaman 001 (Integr., 2021)

Implementation of Symmetric Functions Using Memristive Nanocrossbar Arrays and their Application in Cryptography. - Subhashree Basu; Malay Kule; Hafizur Rahaman 001 (J. Circuits Syst. Comput., 2021)

High Performance Kernel Architecture for Convolutional Neural Network Acceleration. - Anakhi Hazarika; Soumyajit Poddar; Hafizur Rahaman 001 (J. Circuits Syst. Comput., 2021)

Droplet Transportation in MEDA-Based Biochips: An Enhanced Technique for Intelligent Cross-Contamination Avoidance. - Pampa Howladar; Pranab Roy; Hafizur Rahaman 001 (IEEE Trans. Very Large Scale Integr. Syst., 2021)

Testing of Analog Circuits using Statistical and Machine Learning Techniques. - Supriyo Srimani; Hafizur Rahaman 001 (ITC, 2022)

An Online Testing Technique for the Detection of Control Nodes Displacement Faults (CNDF) in Reversible Circuits. - Bappaditya Mondal; Udit Narayana Kar; Chandan Bandyopadhyay; Debashri Roy; Hafizur Rahaman 001 (VDAT, 2022)

Hardware Design with Real-Time Implementation for Security of Medical Images and EPMR. - Sudip Ghosh 001; Yuvam Bhateja; Joshua Roy Palathinkal; Hafizur Rahaman 001 (Circuits Syst. Signal Process., 2022)

Multi-source data fusion technique for parametric fault diagnosis in analog circuits. - Manas Parai; Supriyo Srimani; Kasturi Ghosh; Hafizur Rahaman 001 (Integr., 2022)

DFT with Universal Test Set for All Missing Gate Faults in Reversible Circuits. - Joyati Mondal; Dipak Kumar Kole; Hafizur Rahaman 001; Debesh Kumar Das; Bhargab B. Bhattacharya (J. Circuits Syst. Comput., 2022)

Frequency-scaled thermal-aware test scheduling for 3D ICs using machine learning based temperature estimation. - Subhajit Chatterjee; Surajit Kumar Roy; Chandan Giri; Hafizur Rahaman 001 (Microelectron. J., 2022)

An improved synthesis technique for optical circuits using MIG and XMG. - Rakesh Das; Chandan Bandyopadhyay; Hafizur Rahaman 001 (Microelectron. J., 2022)

MEDA Based Biochips: Detection, Prevention and Rectification Techniques for Cyberphysical Attacks. - Pampa Howladar; Pranab Roy; Hafizur Rahaman 001 (IEEE ACM Trans. Comput. Biol. Bioinform., 2022)

Power and Delay Efficient Hardware Implementation with ATPG for Vedic Multiplier Using Urdhva Tiryagbhyam Sutra. - Anchit Arun; Ananya Chakraborty; Priyanka Dutta 004; Debajyoti Pal; Tridibesh Nag; Debashis De; Sudip Ghosh 001; Hafizur Rahaman 001 (IAIT, 2023)

Hardware Performance Analysis of N-bit CLA on FPGA and Programmable SoC. - Piyali Saha; Sudip Ghosh 001; Debajyoti Pal; Hafizur Rahaman 001 (IAIT, 2023)

A comprehensive review on ReRAM-based accelerators for deep learning. - Pooja Joshi; Hafizur Rahaman 001 (ISDCS, 2023)

Memristor based In-Memory Computing for Edge AI Applications. - Pooja Joshi; Hafizur Rahaman 001 (ISDCS, 2023)

Implementation of Area Efficient Adders for Inexact Computing. - Rounak Roy; Sudip Ghosh 001; Hafizur Rahaman 001 (ISDCS, 2023)

Electrothermal modeling of Multilayer Graphene Nanoribbon (MLGNR) Interconnect considering Energy-per-Layer Screening. - Santasri Giri Tunga; Subhajit Das 001; Sandip Bhattacharya; Hafizur Rahaman 001 (ISDCS, 2023)

Fault Testing in AI-Accelerators: A Review. - Bhargab B. Bhattacharya; Debesh K. Das; Subhajit Chatterjee; Hafizur Rahaman 001 (ATS, 2024)

Droplet Routing in Digital Microfluidic Biochip using Agglomerative Hierarchical Clustering. - Jayanti Das; Indrajit Pan; Hafizur Rahaman 001 (DoSIER, 2024)

A Logic Testing Approach for Hardware Trojan Detection Using Nature Inspired Algorithms. - Banalata Bhunia; Debarshi Dey; Malay Kule; Hafizur Rahaman 001 (ISED, 2024)

Parametric Fault Diagnosis of Analog Circuits using Adaptive Boosting. - Supriyo Srimani; Kasturi Ghosh; Hafizur Rahaman 001 (ISVLSI, 2024)

An Improved Circuit Transformation Technique for Nearest Neighbor Implementation of Quantum Circuits. - Sourodeep Kundu; Subham Kumar; Laxmidhar Biswal; Chandan Bandyopadhyay; Anirban Bhattacharjee; Hafizur Rahaman 001 (VDAT, 2024)

Optimization and Security of AI Models for Deployment at Edge: A Comprehensive Review. - Hafizur Rahaman 001; Chandan Giri; Surajit Kumar Roy; Amlan Chakrabarti (ISVLSI, 2025)