Encountering gate oxide breakdown with shadow transistors to increase reliability. - Claas Cornelius; Frank Sill; Hagen Sämrow; Jakob Salzmann; Dirk Timmermann; Diógenes Cecilio da Silva Jr. (SBCCI, 2008)

Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdown. - Hagen Sämrow; Claas Cornelius; Frank Sill; Andreas Tockhorn; Dirk Timmermann (SBCCI, 2009)

Modeling temperature distribution in Networks-on-Chip using RC-circuits. - Andreas Tockhorn; Claas Cornelius; Hagen Sämrow; Dirk Timmermann (DDECS, 2010)

Functional enhancements of TMR for power efficient and error resilient ASIC designs. - Hagen Sämrow; Claas Cornelius; Philipp Gorski; Jakob Salzmann; Andreas Tockhorn; Dirk Timmermann (DDECS, 2011)

Selective redundancy to improve reliability and to slow down delay degradation due to gate oxide breakdown. - Hagen Sämrow; Claas Cornelius; Philipp Gorski; Andreas Tockhorn; Dirk Timmermann (DDECS, 2012)

Effiziente Simulation von Gateoxiddefekten auf Gatterebene mit Transistorlevel-Genauigkeit. - Hagen Sämrow; Claas Cornelius; Philipp Gorski; Jakob Salzmann; Dirk Timmermann (MBMV, 2012)