A 576 Mb DRAM with 16-channel 10.3125Gbps serial I/O and 14.5 ns latency. - Socrates D. Vamvakos; Bendik Kleveland; Dipak K. Sikdar; B. K. Ahuja; Haidang Lin; Jayaprakash Balachandran; Wignes Balakrishnan; Aldo Bottelli; Jawji Chen; Xiaole Chen; Jae Choi; Jeong Choi; et al. (ESSCIRC, 2012)

A 8.125-15.625 Gb/s SerDes using a sub-sampling ring-oscillator phase-locked loop. - Socrates D. Vamvakos; Charles Boecker; Eric Groen; Alvin Wang; Shaishav Desai; Scott Irwin; Vithal Rao; Aldo Bottelli; Jawji Chen; Xiaole Chen; Prashant Choudhary; Kuo-Chiang Hsieh; et al. (CICC, 2014)

6.3 A 10-to-112Gb/s DSP-DAC-Based Transmitter with 1.2Vppd Output Swing in 7nm FinFET. - Eric Groen; Charlie Boecker; Masum Hossain; Roxanne Vu; Socrates D. Vamvakos; Haidang Lin; Simon Li; Marcus van Ierssel; Prashant Choudhary; Nanyan Wang; Masumi Shibata; Mohammad Hossein Taghavi; et al. (ISSCC, 2020)

A 4×112 Gb/s ADC-DSP Based Multistandard Receiver in 7nm FinFET. - Haidang Lin; Charles Boecker; Masum Hossain; Shankar Tangirala; Roxanne Vu; Socrates D. Vamvakos; Eric Groen; Simon Li; Prashant Choudhary; Nanyan Wang; Masumi Shibata; Hossein Taghavi; et al. (VLSI Circuits, 2020)

10-to-112-Gb/s DSP-DAC-Based Transmitter in 7-nm FinFET With Flex Clocking Architecture. - Eric Groen; Charlie Boecker; Masum Hossain; Roxanne Vu; Socrates D. Vamvakos; Haidang Lin; Simon Li; Marcus van Ierssel; Prashant Choudhary; Nanyan Wang; Masumi Shibata; Mohammad Hossein Taghavi; et al. (IEEE J. Solid State Circuits, 2021)

ADC-DSP-Based 10-to-112-Gb/s Multi-Standard Receiver in 7-nm FinFET. - Haidang Lin; Charlie Boecker; Masum Hossain; Shankar Tangirala; Roxanne Vu; Socrates D. Vamvakos; Eric Groen; Simon Li; Prashant Choudhary; Nanyan Wang; Masumi Shibata; Hossein Taghavi; et al. (IEEE J. Solid State Circuits, 2021)