A Semi-Floating Gate Transistors In-Memory Computing design with 40.14 TOPS/W for matrix-multiplication with frequently updated weight. - Yukai Lin; Yu Wang; Xianwu Hu; Jiayun Feng; Gan Wen; Xiankui Xiong; Haidong Tian; Yufeng Xie (ASICON, 2021)

An Energy Efficient Computing-in-Memory Accelerator With 1T2R Cell and Fully Analog Processing for Edge AI Applications. - Keji Zhou; Chenyang Zhao 008; Jinbei Fang; Jingwen Jiang; Deyang Chen; Yujie Huang; Ming-e Jing; Jun Han 003; Haidong Tian; Xiankui Xiong; Qi Liu 010; Xiaoyong Xue; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A 1T2R1C ReRAM CIM Accelerator With Energy-Efficient Voltage Division and Capacitive Coupling for CNN Acceleration in AI Edge Applications. - Deyang Chen; Zhiwang Guo; Jinbei Fang; Chenyang Zhao 008; Jingwen Jiang; Keji Zhou; Haidong Tian; Xiankui Xiong; Xiaoyong Xue; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An Emerging NVM CIM Accelerator With Shared-Path Transpose Read and Bit-Interleaving Weight Storage for Efficient On-Chip Training in Edge Devices. - Zhiwang Guo; Deyang Chen; Chenyang Zhao 008; Jinbei Fang; Jingwen Jiang; Yixuan Liu; Haidong Tian; Xiankui Xiong; Keji Zhou; Xiaoyong Xue; Qi Liu 010; Xiaoyang Zeng (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

ARCTIC: Agile and Robust Compute-In-Memory Compiler with Parameterized INT/FP Precision and Built-In Self Test. - Hongyi Zhang; Haozhe Zhu; Siqi He; Mengjie Li; Chengchen Wang; Xiankui Xiong; Haidong Tian; Xiaoyang Zeng; Chixiao Chen (DATE, 2024)