FPGA interconnect design using logical effort. - Haile Yu; Yuk Hei Chan; Philip Heng Wai Leong (FPGA, 2008)

FPGA interconnect sizing using extended logical effort model. - Haile Yu (FPL, 2008)

Towards a unique FPGA-based identification circuit using process variations. - Haile Yu; Philip Heng Wai Leong; Heiko Hinkelmann; Leandro Möller; Manfred Glesner; Peter Zipf (FPL, 2009)

A detailed delay path model for FPGAs. - Eddie Hung; Steven J. E. Wilton; Haile Yu; Thomas C. P. Chau; Philip Heng Wai Leong (FPT, 2009)

An FPGA chip identification generator using configurable ring oscillator. - Haile Yu; Philip Heng Wai Leong; Qiang Xu 001 (FPT, 2010)

Fine-grained characterization of process variation in FPGAs. - Haile Yu; Qiang Xu 001; Philip Heng Wai Leong (FPT, 2010)

On timing yield improvement for FPGA designs using architectural symmetry (abstract only). - Haile Yu; Qiang Xu 001; Philip Heng Wai Leong (FPGA, 2011)

On Timing Yield Improvement for FPGA Designs Using Architectural Symmetry. - Haile Yu; Qiang Xu 001; Philip Heng Wai Leong (FPL, 2011)

CODA: A concurrent online delay measurement architecture for critical paths. - Yubin Zhang; Haile Yu; Qiang Xu 001 (ASP-DAC, 2012)

HTOutlier: Hardware Trojan detection with side-channel signature outlier identification. - Jie Zhang 046; Haile Yu; Qiang Xu 001 (HOST, 2012)

An FPGA Chip Identification Generator Using Configurable Ring Oscillators. - Haile Yu; Philip Heng Wai Leong; Qiang Xu 001 (IEEE Trans. Very Large Scale Integr. Syst., 2012)