Cellwise OPC Based on Reduced Standard Cell Library. - Hailong Jiao; Lan Chen (ISQED, 2008)

Smooth awakenings: Reactivation noise suppressed low-leakage and robust MTCMOS flip-flops. - Hailong Jiao; Volkan Kursun (ISCAS, 2010)

Reactivation noise suppression with threshold voltage tuning in sequential MTCMOS circuits. - Hailong Jiao; Volkan Kursun (VLSI-SoC, 2010)

Tri-mode Operation for Noise Reduction and Data Preservation in Low-Leakage Multi-Threshold CMOS Circuits. - Hailong Jiao; Volkan Kursun (VLSI-SoC (Selected Papers), 2010)

Low-Leakage and Compact Registers with Easy-Sleep Mode. - Hailong Jiao; Volkan Kursun (J. Low Power Electron., 2010)

Ground-Bouncing-Noise-Aware Combinational MTCMOS Circuits. - Hailong Jiao; Volkan Kursun (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

Sleep signal slew rate modulation for mode transition noise suppression in ground gated integrated circuits. - Hailong Jiao; Volkan Kursun (SoCC, 2011)

Noise-Aware Data Preserving Sequential MTCMOS Circuits with Dynamic Forward Body Bias. - Hailong Jiao; Volkan Kursun (J. Circuits Syst. Comput., 2011)

Ground Bouncing Noise Suppression Techniques for Data Preserving Sequential MTCMOS Circuits. - Hailong Jiao; Volkan Kursun (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Full-custom design of low leakage data preserving ground gated 6T SRAM cells to facilitate single-ended write operations. - Hailong Jiao; Volkan Kursun (ISCAS, 2012)

Multi-phase sleep signal modulation for mode transition noise mitigation in MTCMOS circuits. - Hailong Jiao; Volkan Kursun (ISOCC, 2012)

Threshold Voltage Tuning for Faster Activation With Lower Noise in Tri-Mode MTCMOS Circuits. - Hailong Jiao; Volkan Kursun (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Low-leakage hybrid FinFET SRAM cell with asymmetrical gate overlap / underlap bitline access transistors for enhanced read data stability. - Shairfe Muhammad Salahuddin; Hailong Jiao; Volkan Kursun (ISCAS, 2013)

A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability. - Shairfe Muhammad Salahuddin; Hailong Jiao; Volkan Kursun (ISQED, 2013)

Ground gated 8T SRAM cells with enhanced read and hold data stability. - Hailong Jiao; Volkan Kursun (ISVLSI, 2013)

An electrostatically-driven and capacitively-sensed differential lateral resonant pressure microsensor. - Bo Xie 006; Hailong Jiao; Junbo Wang 002; Deyong Chen; Jian Chen 012 (NEMS, 2013)

Characterization of mode transition timing overhead for net energy savings in low-noise MTCMOS circuits. - Hailong Jiao; Volkan Kursun (VLSI-SoC, 2013)

Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits. - Hailong Jiao; Volkan Kursun (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Low-leakage 9-CN-MOSFET SRAM cell with enhanced read and write voltage margins. - Yanan Sun 003; Hailong Jiao; Volkan Kursun (ICM, 2014)

Mode transition timing and energy overhead analysis in noise-aware MTCMOS circuits. - Hailong Jiao; Volkan Kursun (Microelectron. J., 2014)

Memristor based computation-in-memory architecture for data-intensive applications. - Said Hamdioui; Lei Xie 005; Hoang Anh Du Nguyen; Mottaqiallah Taouil; Koen Bertels; Henk Corporaal; Hailong Jiao; Francky Catthoor; Dirk J. Wouters; Eike Linn; Jan van Lunteren (DATE, 2015)

A Novel Robust and Low-Leakage SRAM Cell With Nine Carbon Nanotube Transistors. - Yanan Sun 003; Hailong Jiao; Volkan Kursun (IEEE Trans. Very Large Scale Integr. Syst., 2015)

IEEE Std P1838: DfT standard-under-development for 2.5D-, 3D-, and 5.5D-SICs. - Erik Jan Marinissen; Teresa L. McLaurin; Hailong Jiao (ETS, 2016)

Variations-tolerant 9T SRAM circuit with robust and low leakage SLEEP mode. - Hailong Jiao; Yongmin Qiu; Volkan Kursun (IOLTS, 2016)

Variability-aware 7T SRAM circuit with low leakage high data stability SLEEP mode. - Hailong Jiao; Yongmin Qiu; Volkan Kursun (Integr., 2016)

Low power and robust memory circuits with asymmetrical ground gating. - Hailong Jiao; Yongmin Qiu; Volkan Kursun (Microelectron. J., 2016)

Metallic-carbon-nanotube-removal tolerant SRAM cell with 9 transistors. - Yanan Sun 003; Weifeng He; Zhigang Mao; Hailong Jiao; Volkan Kursun (ASICON, 2017)

An improved NLOS error elimination algorithm for indoor ultra-wideband localization. - Peng Ling; Chong Shen 002; Kun Zhang 011; Hailong Jiao; Liqiang Zheng; Xi Deng (IEEE SENSORS, 2017)

An analytical model for interdependent setup/hold-time characterization of flip-flops. - Hadi Ahmadi Balef; Hailong Jiao; José Pineda de Gyvez; Kees Goossens (ISQED, 2017)

Reconfigurable Support Vector Machine Classifier with Approximate Computing. - Martin Van Leussen; Jos Huisken; Lei Wang; Hailong Jiao; José Pineda de Gyvez (ISVLSI, 2017)

Embedded toggle generator to control the switching activity during test of digital 2D-SoCs and 3D-SICs. - Leonidas Katselas; Hailong Jiao; Angelos Athanasiadis; Christos Papameletis; Alkis A. Hatzopoulos; Erik Jan Marinissen (PATMOS, 2017)

Datawidth-Aware Energy-Efficient Multipliers: A Case for Going Sign Magnitude. - Luc Waeijen; Hailong Jiao; Henk Corporaal; Yifan He 002 (DSD, 2018)

IEEE Std P1838's flexible parallel port and its specification with Google's protocol buffers. - Yu Li 007; Ming Shao; Hailong Jiao; Adam Cron; Sandeep Bhatia; Erik Jan Marinissen (ETS, 2018)

Multi-Bit Pulsed-Latch Based Low Power Synchronous Circuit Design. - Kamlesh Singh; Omar Alejandro Rodriguez Rosas; Hailong Jiao; Jos Huisken; José Pineda de Gyvez (ISCAS, 2018)

Low power latch based design with smart retiming. - Kamlesh Singh; Hailong Jiao; Jos Huisken; Hamed Fatemi; José Pineda de Gyvez (ISQED, 2018)

Achieving Low Power Classification with Classifier Ensemble. - Fanglei Hu; Min Zhang 041; Hailong Jiao (ISVLSI, 2018)

On-Chip Toggle Generators to Provide Realistic Conditions during Test of Digital 2D-SoCs and 3D-SICs. - Leonidas Katselas; Alkis A. Hatzopoulos; Hailong Jiao; Christos Papameletis; Erik Jan Marinissen (ITC, 2018)

Understanding the Impact of Circuit-Level Inaccuracy on Sensor Network Performance. - Paul Detterer; Cumhur Erdin; Majid Nabi; Twan Basten; Hailong Jiao (PE-WASUN, 2018)

Crosstalk-noise-aware bus coding with low-power ground-gated repeaters. - Hailong Jiao; Rui Wang; Yifan He 002 (Int. J. Circuit Theory Appl., 2018)

Trading Digital Accuracy for Power in an RSSI Computation of a Sensor Network Transceiver. - Paul Detterer; Cumhur Erdin; Majid Nabi; José Pineda de Gyvez; Twan Basten; Hailong Jiao (DATE, 2019)

Statistical Modeling and Design of a 16nm 9T SRAM Cell Considering Post-Synthesis Removal of Metallic Carbon-Nanotubes. - Yanan Sun 003; Weifeng He; Zhigang Mao; Hailong Jiao; Volkan Kursun (ICEIC, 2019)

Standard Cell Optimization for Ultra-Low-Voltage Digital Circuits. - Yuting Chen; Hailong Jiao (ICICDT, 2019)

A 12T Low-Power Standard-Cell Based SRAM Circuit for Ultra-Low-Voltage Operations. - Jiacong Sun; Hailong Jiao (ICICDT, 2019)

Low Power Karnaugh Map Approximate Adder for Error Compensation in Loop Accumulations. - Chunmei Yang; Hailong Jiao (ICICDT, 2019)

A Compact Low-Voltage Segmented D/A Converter with Adjustable Gamma Coefficient for AMOLED Displays. - Xinxin Huo; Wenlong Bai; Hing-Mo Lam; Congwei Liao; Min Zhang 041; Shengdong Zhang; Hailong Jiao (ISCAS, 2019)

Voltage Stacked Design of a Microcontroller for Near/Sub-threshold Operation. - Kamlesh Singh; Barry de Bruin; Jos Huisken; Hailong Jiao; José Pineda de Gyvez (SoCC, 2019)

Trading Sensitivity for Power in an IEEE 802.15.4 Conformant Adequate Demodulator. - Paul Detterer; Cumhur Erdin; Jos Huisken; Hailong Jiao; Majid Nabi; Twan Basten; José Pineda de Gyvez (DATE, 2020)

A Compact Low-Power Data Retention Flip-Flop with Easy-Sleep Mode. - Hailong Jiao; Zhanliang Zhang (ISCAS, 2020)

A Compensation System using Analog Voltage Adder with Continuous Output for AMOLED Display Drivers. - Hezi Qiu; Jian Liang; Wenlong Bai; Hing-Mo Lam; Junjun An; Congwei Liao; Min Zhang 041; Hailong Jiao; Shengdong Zhang (ISCAS, 2020)

A -80 dB PSRR 4.99 ​ppm/°C TC bandgap reference with nonlinear compensation. - Jian Liang; Shuiping Yi; Wenlong Bai; Lidan Wang 001; Chenchang Zhan; Congwei Liao; Hing-Mo Lam; Min Zhang 041; Shengdong Zhang; Hailong Jiao (Microelectron. J., 2020)

Monolithic 3D Carbon Nanotube Memory for Enhanced Yield and Integration Density. - Yanan Sun 003; Weifeng He; Zhigang Mao; Hailong Jiao; Volkan Kursun (IEEE Trans. Circuits Syst. I Regul. Pap., 2020)

Efficient Zero-Activation-Skipping for On-Chip Low-Energy CNN Acceleration. - Min Liu; Yifan He 002; Hailong Jiao (AICAS, 2021)

An Energy-Efficient Low-Latency 3D-CNN Accelerator Leveraging Temporal Locality, Full Zero-Skipping, and Hierarchical Load Balance. - Changchun Zhou 001; Min Liu; Siyuan Qiu; Yifan He 002; Hailong Jiao (DAC, 2021)

Insights of 3D Input CNN in EEG-based Emotion Recognition. - Kris van Noord; Wenjin Wang 002; Hailong Jiao (EMBC, 2021)

Segmented Reconfigurable Cyclic Shifter for QC-LDPC Decoder. - Hing-Mo Lam; Silin Lu; Hezi Qiu; Hailong Jiao; Min Zhang 041; Shengdong Zhang (ISCAS, 2021)

A Pull-Up Adaptive Sense Amplifier Based on Dual-Gate IGZO TFTs. - Silin Lu; Lei Lu; Shengdong Zhang; Hailong Jiao (ISCAS, 2021)

A Hybrid Digital Transmitter Architecture for High- Efficiency and High-Speed Applications. - Chen Xu; Xiaolei Su; Zhengkun Shen; Dong Wang; Yi Tan; Zexue Liu; Hailong Jiao; Junhua Liu; Huailin Liao (ISCAS, 2021)

Receiver-Sensitivity Control for Energy-Efficient IoT Networks. - Paul Detterer; Majid Nabi; Hailong Jiao; Twan Basten (IEEE Commun. Lett., 2021)

A 3.36-GHz Locking-Tuned Type-I Sampling PLL With -78.6-dBc Reference Spur Merging Single-Path Reference-Feedthrough-Suppression and Narrow-Pulse-Shielding Techniques. - Yunbo Huang; Yong Chen 005; Hailong Jiao; Pui-In Mak; Rui Paulo Martins (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Pseudo Multi-Port SRAM Circuit for Image Processing in Display Drivers. - Hing-Mo Lam; Fan Guo; Hezi Qiu; Min Zhang 041; Hailong Jiao; Shengdong Zhang (IEEE Trans. Circuits Syst. Video Technol., 2021)

Converter-Free Power Delivery Using Voltage Stacking for Near/Subthreshold Operation. - Kamlesh Singh; Barry de Bruin; Hailong Jiao; Jos Huisken; Henk Corporaal; José Pineda de Gyvez (IEEE Trans. Very Large Scale Integr. Syst., 2021)

An LUT-Based Multiplier Array for Systolic Array-Based Convolutional Neural Network Accelerator. - Ming Liu 022; Yifan He 002; Hailong Jiao (APCCAS, 2022)

Ternary In-Memory MAC Accelerator With Dual-6T SRAM Cell for Deep Neural Networks. - Xudong Wang; Geng Li; Jiacong Sun; Huanjie Fan; Yong Chen; Hailong Jiao (APCCAS, 2022)

A Karnaugh Map Approximate Adder With Intrinsic Error Compensation. - Chenyu Xie; Chunmei Yang; Hailong Jiao (APCCAS, 2022)

Guest Editors' Introduction: Special Issue on Design and Test of Multidie Packages. - Adam Cron; Hailong Jiao; Erik Jan Marinissen (IEEE Des. Test, 2022)

Receiver Design With an Adjustable Energy-Signal-Quality Tradeoff for IoT Networks. - Paul Detterer; Majid Nabi; Hailong Jiao; Twan Basten (IEEE Internet Things J., 2022)

An Ultra-Low-Voltage Bit-Interleaved Synthesizable 13T SRAM Circuit. - Jiacong Sun; Hao Guo; Geng Li; Hailong Jiao (IEEE J. Solid State Circuits, 2022)

A High-Efficiency Segmented Reconfigurable Cyclic Shifter for 5G QC-LDPC Decoder. - Hing-Mo Lam; Silin Lu; Hezi Qiu; Min Zhang 041; Hailong Jiao; Shengdong Zhang (IEEE Trans. Circuits Syst. I Regul. Pap., 2022)

A Bypassable Scan Flip-Flop for Low Power Testing With Data Retention Capability. - Xugang Cao; Hailong Jiao; Erik Jan Marinissen (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

An Ultralow-Power 65-nm Standard Cell Library for Near/Subthreshold Digital Circuits. - Yuting Chen; Yuxuan Nie; Hailong Jiao (IEEE Trans. Very Large Scale Integr. Syst., 2022)

An Energy-Efficient 3D Point Cloud Neural Network Accelerator With Efficient Filter Pruning, MLP Fusion, and Dual-Stream Sampling. - Changchun Zhou 001; Yuzhe Fu; Min Liu; Siyuan Qiu; Ge Li; Yifan He 002; Hailong Jiao (ICCAD, 2023)

Sagitta: An Energy-Efficient Sparse 3D-CNN Accelerator for Real-Time 3-D Understanding. - Changchun Zhou 001; Min Liu; Siyuan Qiu; Xugang Cao; Yuzhe Fu; Yifan He 002; Hailong Jiao (IEEE Internet Things J., 2023)

LightSeizureNet: A Lightweight Deep Learning Model for Real-Time Epileptic Seizure Detection. - Siyuan Qiu; Wenjin Wang 002; Hailong Jiao (IEEE J. Biomed. Health Informatics, 2023)

C3MLS: An Ultra-Wide-Range Energy-Efficient Level Shifter With CCLS/CMLS Hybrid Structure. - Cong Huang; Hailong Jiao (IEEE J. Solid State Circuits, 2023)

APCCAS 2022 Guest Editorial Special Issue Based on the 18th Asia Pacific Conference on Circuits and Systems. - Xiaojin Zhao; Hailong Jiao; Wei Mao 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

CNN Accelerator at the Edge With Adaptive Zero Skipping and Sparsity-Driven Data Flow. - Ming Liu 022; Changchun Zhou 001; Siyuan Qiu; Yifan He 002; Hailong Jiao (IEEE Trans. Circuits Syst. Video Technol., 2023)

A Low-Power Single-Phase Split-Controlled Flip-Flop With No Redundant Switching. - Zhuoya Yan; Yingna Huang; Hailong Jiao (ISCAS, 2024)

Adjustable Multi-Stream Block-Wise Farthest Point Sampling Acceleration in Point Cloud Analysis. - Changchun Zhou 001; Yuzhe Fu; Yanzhe Ma; Eryi Han; Yifan He 002; Hailong Jiao (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

SoftAct: A High-Precision Softmax Architecture for Transformers Supporting Nonlinear Functions. - Yuzhe Fu; Changchun Zhou 001; Tianling Huang; Eryi Han; Yifan He 002; Hailong Jiao (IEEE Trans. Circuits Syst. Video Technol., 2024)

Rate-Distortion Optimized Motion Estimation for Dynamic Point Cloud Geometry Compression. - Qi Zhang 029; Yiting Shao; Lixuan Meng; Hailong Jiao; Shan Liu 001; Ge Li 002 (DCC, 2025)

23.4 Nebula: A 28nm 109.8TOPS/W 3D PNN Accelerator Featuring Adaptive Partition, Multi-Skipping, and Block-Wise Aggregation. - Changchun Zhou 001; Tianling Huang; Yanzhe Ma; Yuzhe Fu; Xiangjie Song; Siyuan Qiu; Jiacong Sun; Min Liu; Ge Li; Yifan He 002; Yuchao Yang 001; Hailong Jiao (ISSCC, 2025)

Automatic epileptic seizure detection with an ultra lightweight 3D-CNN model. - Chenyu Xie; Siyuan Qiu; Changchun Zhou 001; Xiaoyan Song; Jie Yang 083; Jia Huang; Wenjin Wang 002; Hailong Jiao (Biomed. Signal Process. Control., 2025)

A Two-Stage Prediction + Detection Framework for Real-Time Epileptic Seizure Monitoring. - Siyuan Qiu; Wenjin Wang 002; Changchun Zhou 001; Xiaoyan Song; Jie Yang 083; Hailong Jiao (IEEE Trans. Instrum. Meas., 2025)

Robust Monolithic 3D Carbon-Based Computing-in-SRAM With Variation-Aware Bit-Wise Data-Mapping for High-Performance and Integration Density. - Dengfeng Wang; Weifeng He; Qin Wang 009; Hailong Jiao; Yanan Sun 003 (IEEE Trans. Circuits Syst. I Regul. Pap., 2025)