Hailong Yao

Orcid: 0000-0002-8750-3086

According to our database¹, Hailong Yao authored at least 81 papers between 2004 and 2023.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

Timeline

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In proceedings

Article

PhD thesis

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On csauthors.net:

Bibliography

2023

A Cooperative Multiagent Reinforcement Learning Framework for Droplet Routing in Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2023

TAEM 2.0: A Faster Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

NeuroEscape: Ordered Escape Routing via Monte-Carlo Tree Search and Neural Network.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

SOAER: Self-Obstacle Avoiding Escape Routing for Paper-Based Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

GAT-based Concentration Prediction for Random Microfluidic Mixers with Multiple Input Flow Rates.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

A Compilation Toolchain of Neural Networks for FPGA Backend.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

Contamination-Aware Synthesis for Programmable Microfluidic Devices.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

ECC-based lightweight authentication and access control scheme for IoT E-healthcare.

[BibT_eX]

[DOI]

Soft Comput., 2022

NeuroSchedule: A Novel Effective GNN-based Scheduling Method for High-level Synthesis.

[BibT_eX]

[DOI]

Jun Zeng

Mingyang Kou

Hailong Yao

Proceedings of the Advances in Neural Information Processing Systems 35: Annual Conference on Neural Information Processing Systems 2022, 2022

KunlunTVM: A Compilation Framework for Kunlun Chip Supporting Both Training and Inference.

[BibT_eX]

[DOI]

Jun Zeng

Mingyang Kou

Hailong Yao

Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

GEML: GNN-based efficient mapping method for large loop applications on CGRA.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

GNN-based concentration prediction for random microfluidic mixers.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

2021

DCSA: Distributed Channel-Storage Architecture for Flow-Based Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Splitter-Aware Multiterminal Routing With Length-Matching Constraint for RSFQ Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

A certificateless linearly homomorphic signature scheme for network coding and its application in the IoT.

[BibT_eX]

[DOI]

Bin Wu

Caifen Wang

Hailong Yao

Peer-to-Peer Netw. Appl., 2021

Concentration Gradients Enhancement of Christmas-Tree Structure Based on a Look-Up Table.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

Machine Learning Based Acceleration Method for Ordered Escape Routing.

[BibT_eX]

[DOI]

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020

Multicontrol: Advanced Control-Logic Synthesis for Flow-Based Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

URBER: Ultrafast Rule-Based Escape Routing Method for Large-Scale Sample Delivery Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Integrated Control-Fluidic Codesign Methodology for Paper-Based Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Lookup Table-Based Fast Reliability-Aware Sample Preparation Using Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Microfluidic Design for Concentration Gradient Generation Using Artificial Neural Network.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Impersonation Attacks on Lightweight Anonymous Authenticated Key Exchange Scheme for IoT.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

Leveled Adaptively Strong-Unforgeable Identity-Based Fully Homomorphic Signatures.

[BibT_eX]

[DOI]

Caifen Wang

Bin Wu

Hailong Yao

IEEE Access, 2020

TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA.

[BibT_eX]

[DOI]

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

Transfer Learning-Based Microfluidic Design System for Concentration Generation∗.

[BibT_eX]

[DOI]

Weiqing Ji

Tsung-Yi Ho

Hailong Yao

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

Design Methodology for TFT-Based Pseudo-CMOS Logic Array With Multilayer Interconnection Architecture and Optimization Algorithms.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

A Privacy-Preserving RLWE-Based Remote Biometric Authentication Scheme for Single and Multi-Server Environments.

[BibT_eX]

[DOI]

IEEE Access, 2019

Automatic Breast Cancer Grading of Histological Images using Dilated Residual Network.

[BibT_eX]

[DOI]

Yanyuet Man

Hailong Yao

Proceedings of the 11th International Conference on Bioinformatics and Biomedical Technology, 2019

Cryptanalysis and Improvement of a Remote Anonymous Authentication Protocol for Mobile Multi-server Environments.

[BibT_eX]

[DOI]

Proceedings of the Fourth IEEE International Conference on Data Science in Cyberspace, 2019

2018

Revisiting Routability-Driven Placement for Analog and Mixed-Signal Circuits.

[BibT_eX]

[DOI]

Hongxia Zhou

Chiu-Wing Sham

Hailong Yao

ACM Trans. Design Autom. Electr. Syst., 2018

AARF: Any-Angle Routing for Flow-Based Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Physical Co-Design of Flow and Control Layers for Flow-Based Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

A Comprehensive Security System for Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference in Asia, 2018

More Effective Randomly-Designed Microfluidics.

[BibT_eX]

[DOI]

Weiqing Ji

Tsung-Yi Ho

Hailong Yao

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

An Approach to Information Fusion and Group Deecision Making Based on Choquet Integral Operators for Interval-Valued Intuitionistic Fuzzy Data.

[BibT_eX]

[DOI]

Bo Hai

Hailong Yao

Proceedings of the 2018 International Conference on Machine Learning and Cybernetics, 2018

Multi-channel and fault-tolerant control multiplexing for flow-based microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

A Novel Blockchain-Based Authenticated Key Exchange Protocol and Its Applications.

[BibT_eX]

[DOI]

Hailong Yao

Caifen Wang

Proceedings of the Third IEEE International Conference on Data Science in Cyberspace, 2018

2017

Pressure-Aware Control Layer Optimization for Flow-Based Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2017

LUTOSAP: Lookup Table Based Online Sample Preparation in Microfluidic Biochips.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Transport or Store?: Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Close-to-optimal placement and routing for continuous-flow microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Integrated Functional and Washing Routing Optimization for Cross-Contamination Removal in Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Research on path loss and shadow fading of ultra wideband simulation channel.

[BibT_eX]

[DOI]

Hongmei Zhao

Hailong Yao

Shuting Guo

Int. J. Distributed Sens. Networks, 2016

Control-fluidic CoDesign for paper-based digital microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

Sequence-pair-based placement and routing for flow-based microfluidic biochips.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

SIAR: Customized real-time interactive router for analog circuits.

[BibT_eX]

[DOI]

Integr., 2015

Integrated Flow-Control Codesign Methodology for Flow-Based Microfluidic Biochips.

[BibT_eX]

[DOI]

IEEE Des. Test, 2015

SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips.

[BibT_eX]

[DOI]

Proceedings of the 2015 Symposium on International Symposium on Physical Design, ISPD 2015, Monterey, CA, USA, March 29, 2015

PACOR: practical control-layer routing flow with length-matching constraint for flow-based microfluidic biochips.

[BibT_eX]

[DOI]

Hailong Yao

Tsung-Yi Ho

Yici Cai

Proceedings of the 52nd Annual Design Automation Conference, 2015

2014

Length matching in detailed routing for analog and mixed signal circuits.

[BibT_eX]

[DOI]

Microelectron. J., 2014

Fast and scalable parallel layout decomposition in double patterning lithography.

[BibT_eX]

[DOI]

Integr., 2014

Slicing Floorplans with Handling Symmetry and General Placement Constraints.

[BibT_eX]

[DOI]

Hongxia Zhou

Chiu-Wing Sham

Hailong Yao

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Practical Functional and Washing Droplet Routing for Cross-Contamination Avoidance in Digital Microfluidic Biochips.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013

SUALD: Spacing uniformity-aware layout decomposition in triple patterning lithography.

[BibT_eX]

[DOI]

Zihao Chen

Hailong Yao

Yici Cai

Proceedings of the International Symposium on Quality Electronic Design, 2013

A new splitting graph construction algorithm for SIAR router.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

Analog routing considering min-area constraint.

[BibT_eX]

[DOI]

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

LEMAR: A novel length matching routing algorithm for analog and mixed signal circuits.

[BibT_eX]

[DOI]

Hailong Yao

Yici Cai

Qiang Gao

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A novel fine-grain track routing approach for routability and crosstalk optimization.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

A novel detailed routing algorithm with exact matching constraint for analog and mixed signal circuits.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

SIAR: splitting-graph-based interactive analog router.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010

Layout Decomposition Approaches for Double Patterning Lithography.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Analog circuit shielding routing algorithm based on net classification.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010

2009

Revisiting the linear programming framework for leakage power vs. performance optimization.

[BibT_eX]

[DOI]

Kwangok Jeong

Andrew B. Kahng

Hailong Yao

Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

2008

Efficient range pattern matching algorithm for process-hotspot detection.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2008

Layout decomposition for double patterning lithography.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Dose map and placement co-optimization for timing yield enhancement and leakage power reduction.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

2007

CMP-aware Maze Routing Algorithm for Yield Enhancement.

[BibT_eX]

[DOI]

Hailong Yao

Yici Cai

Xianlong Hong

Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

2006

Multilevel Routing With Redundant Via Insertion.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Congestion-driven W-shape multilevel full-chip routing framework.

[BibT_eX]

[DOI]

Hailong Yao

Yici Cai

Xianlong Hong

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Efficient process-hotspot detection using range pattern matching.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

DFM-aware Routing for Yield Enhancement.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005

Crosstalk-Aware Routing Resource Assignment.

[BibT_eX]

[DOI]

J. Comput. Sci. Technol., 2005

Improved multilevel routing with redundant via placement for yield and reliability.

[BibT_eX]

[DOI]

Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

2004

Crosstalk driven routing resource assignment.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

Hailong Yao

Timeline

Legend:

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On csauthors.net:

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