Crosstalk driven routing resource assignment. - Hailong Yao; Qiang Zhou 001; Xianlong Hong; Yici Cai (ISCAS (5), 2004)

Improved multilevel routing with redundant via placement for yield and reliability. - Hailong Yao; Yici Cai; Xianlong Hong; Qiang Zhou 001 (ACM Great Lakes Symposium on VLSI, 2005)

Crosstalk-Aware Routing Resource Assignment. - Hailong Yao; Yici Cai; Qiang Zhou 001; Xianlong Hong (J. Comput. Sci. Technol., 2005)

DFM-aware Routing for Yield Enhancement. - Xianlong Hong; Yici Cai; Hailong Yao; Duo Li (APCCAS, 2006)

Efficient process-hotspot detection using range pattern matching. - Hailong Yao; Subarna Sinha; Charles C. Chiang; Xianlong Hong; Yici Cai (ICCAD, 2006)

Congestion-driven W-shape multilevel full-chip routing framework. - Hailong Yao; Yici Cai; Xianlong Hong (ISCAS, 2006)

Multilevel Routing With Redundant Via Insertion. - Hailong Yao; Yici Cai; Qiang Zhou 001; Xianlong Hong (IEEE Trans. Circuits Syst. II Express Briefs, 2006)

CMP-aware Maze Routing Algorithm for Yield Enhancement. - Hailong Yao; Yici Cai; Xianlong Hong (ISVLSI, 2007)

Dose map and placement co-optimization for timing yield enhancement and leakage power reduction. - Kwangok Jeong; Andrew B. Kahng; Chul-Hong Park; Hailong Yao (DAC, 2008)

Layout decomposition for double patterning lithography. - Andrew B. Kahng; Chul-Hong Park; Xu Xu 001; Hailong Yao (ICCAD, 2008)

Efficient range pattern matching algorithm for process-hotspot detection. - Hailong Yao; Subarna Sinha; Jingyu Xu 001; Charles C. Chiang; Yici Cai; Xianlong Hong (IET Circuits Devices Syst., 2008)

Revisiting the linear programming framework for leakage power vs. performance optimization. - Kwangok Jeong; Andrew B. Kahng; Hailong Yao (ISQED, 2009)

Analog circuit shielding routing algorithm based on net classification. - Qiang Gao; Yin Shen; Yici Cai; Hailong Yao (ISLPED, 2010)

Dose Map and Placement Co-Optimization for Improved Timing Yield and Leakage Power. - Kwangok Jeong; Andrew B. Kahng; Chul-Hong Park; Hailong Yao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Layout Decomposition Approaches for Double Patterning Lithography. - Andrew B. Kahng; Chul-Hong Park; Xu Xu 001; Hailong Yao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010)

Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization. - Feifei Niu; Qiang Zhou 001; Hailong Yao; Yici Cai; Jianlei Yang 001; Chin Ngai Sze (ACM Great Lakes Symposium on VLSI, 2011)

SIAR: splitting-graph-based interactive analog router. - Fan Yang; Hailong Yao; Qiang Zhou 001; Yici Cai (ACM Great Lakes Symposium on VLSI, 2011)

A novel detailed routing algorithm with exact matching constraint for analog and mixed signal circuits. - Qiang Gao; Hailong Yao; Qiang Zhou 001; Yici Cai (ISQED, 2011)

A novel fine-grain track routing approach for routability and crosstalk optimization. - Zhongdong Qi; Qiang Zhou 001; Yanming Jia; Yici Cai; Zhuoyuan Li 003; Hailong Yao (ISQED, 2011)

Minimization of Circuit Delay and Power through Gate Sizing and Threshold Voltage Assignment. - Shuzhe Zhou; Hailong Yao; Qiang Zhou 001; Yici Cai (ISVLSI, 2011)

LEMAR: A novel length matching routing algorithm for analog and mixed signal circuits. - Hailong Yao; Yici Cai; Qiang Gao (ASP-DAC, 2012)

Analog routing considering min-area constraint. - Weijie Chen; Hailong Yao; Yici Cai; Qiang Zhou 001 (ASICON, 2013)

A new splitting graph construction algorithm for SIAR router. - Jinming Zhao; Hailong Yao; Yici Cai; Qiang Zhou 001 (ASICON, 2013)

SUALD: Spacing uniformity-aware layout decomposition in triple patterning lithography. - Zihao Chen; Hailong Yao; Yici Cai (ISQED, 2013)

Practical Functional and Washing Droplet Routing for Cross-Contamination Avoidance in Digital Microfluidic Biochips. - Qin Wang 005; Yiren Shen; Hailong Yao; Tsung-Yi Ho; Yici Cai (DAC, 2014)

Slicing Floorplans with Handling Symmetry and General Placement Constraints. - Hongxia Zhou; Chiu-Wing Sham; Hailong Yao (ISVLSI, 2014)

Fast and scalable parallel layout decomposition in double patterning lithography. - Wei Zhao; Hailong Yao; Yici Cai; Subarna Sinha; Charles C. Chiang (Integr., 2014)

Length matching in detailed routing for analog and mixed signal circuits. - Hailong Yao; Qiang Gao; Yici Cai; Qiang Zhou 001; Chiu-Wing Sham (Microelectron. J., 2014)

PACOR: practical control-layer routing flow with length-matching constraint for flow-based microfluidic biochips. - Hailong Yao; Tsung-Yi Ho; Yici Cai (DAC, 2015)

SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constrained EWOD Chips. - Qin Wang 005; Weiran He; Hailong Yao; Tsung-Yi Ho; Yici Cai (ISPD, 2015)

Integrated Flow-Control Codesign Methodology for Flow-Based Microfluidic Biochips. - Hailong Yao; Qin Wang 005; Yizhong Ru; Yici Cai; Tsung-Yi Ho (IEEE Des. Test, 2015)

SIAR: Customized real-time interactive router for analog circuits. - Hailong Yao; Fan Yang; Yici Cai; Qiang Zhou 001; Chiu-Wing Sham (Integr., 2015)

Obstacle-Avoiding and Slew-Constrained Clock Tree Synthesis With Efficient Buffer Insertion. - Yici Cai; Chao Deng; Qiang Zhou 001; Hailong Yao; Feifei Niu; Cliff N. Sze (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Sequence-pair-based placement and routing for flow-based microfluidic biochips. - Qin Wang 005; Yizhong Ru; Hailong Yao; Tsung-Yi Ho; Yici Cai (ASP-DAC, 2016)

Control-fluidic CoDesign for paper-based digital microfluidic biochips. - Qin Wang 005; Zeyan Li; Haena Cheong; Oh-Sun Kwon; Hailong Yao; Tsung-Yi Ho; Kwanwoo Shin; Bing Li 005; Ulf Schlichtmann; Yici Cai (ICCAD, 2016)

Research on path loss and shadow fading of ultra wideband simulation channel. - Hongmei Zhao; Hailong Yao; Shuting Guo (Int. J. Distributed Sens. Networks, 2016)

Integrated Functional and Washing Routing Optimization for Cross-Contamination Removal in Digital Microfluidic Biochips. - Hailong Yao; Qin Wang 005; Yiren Shen; Tsung-Yi Ho; Yici Cai (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)

Close-to-optimal placement and routing for continuous-flow microfluidic biochips. - Andreas Grimmer; Qin Wang 005; Hailong Yao; Tsung-Yi Ho; Robert Wille (ASP-DAC, 2017)

Hamming-distance-based valve-switching optimization for control-layer multiplexing in flow-based microfluidic biochips. - Qin Wang 005; Shiliang Zuo; Hailong Yao; Tsung-Yi Ho; Bing Li 005; Ulf Schlichtmann; Yici Cai (ASP-DAC, 2017)

Transport or Store?: Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage. - Chunfeng Liu; Bing Li 005; Hailong Yao; Paul Pop; Tsung-Yi Ho; Ulf Schlichtmann (DAC, 2017)

Design Methodology for Thin-Film Transistor Based Pseudo-CMOS Logic Array with Multi-Layer Interconnect Architecture. - Qinghang Zhao; Yongpan Liu; Wenyu Sun; Jiaqing Zhao; Hailong Yao; Xiaojun Guo; Huazhong Yang (DAC, 2017)

LUTOSAP: Lookup Table Based Online Sample Preparation in Microfluidic Biochips. - Lingxuan Shao; Yibin Yang 001; Hailong Yao; Tsung-Yi Ho; Yici Cai (ACM Great Lakes Symposium on VLSI, 2017)

Pressure-Aware Control Layer Optimization for Flow-Based Microfluidic Biochips. - Qin Wang 005; Yue Xu; Shiliang Zuo; Hailong Yao; Tsung-Yi Ho; Bing Li 005; Ulf Schlichtmann; Yici Cai (IEEE Trans. Biomed. Circuits Syst., 2017)

A Novel Blockchain-Based Authenticated Key Exchange Protocol and Its Applications. - Hailong Yao; Caifen Wang (DSC, 2018)

Multi-channel and fault-tolerant control multiplexing for flow-based microfluidic biochips. - Ying Zhu 008; Bing Li 005; Tsung-Yi Ho; Qin Wang 005; Hailong Yao; Robert Wille; Ulf Schlichtmann (ICCAD, 2018)

An Approach to Information Fusion and Group Deecision Making Based on Choquet Integral Operators for Interval-Valued Intuitionistic Fuzzy Data. - Bo Hai; Hailong Yao (ICMLC, 2018)

More Effective Randomly-Designed Microfluidics. - Weiqing Ji; Tsung-Yi Ho; Hailong Yao (ISVLSI, 2018)

A Comprehensive Security System for Digital Microfluidic Biochips. - Chun-Yu Lin; Juinn-Dar Huang; Hailong Yao; Tsung-Yi Ho (ITC-Asia, 2018)

Physical Co-Design of Flow and Control Layers for Flow-Based Microfluidic Biochips. - Qin Wang 005; Hao Zou 001; Hailong Yao; Tsung-Yi Ho; Robert Wille; Yici Cai (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

AARF: Any-Angle Routing for Flow-Based Microfluidic Biochips. - Kailin Yang; Hailong Yao; Tsung-Yi Ho; Kunze Xin; Yici Cai (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018)

Revisiting Routability-Driven Placement for Analog and Mixed-Signal Circuits. - Hongxia Zhou; Chiu-Wing Sham; Hailong Yao (ACM Trans. Design Autom. Electr. Syst., 2018)

Cryptanalysis and Improvement of a Remote Anonymous Authentication Protocol for Mobile Multi-server Environments. - Hailong Yao; Xingbing Fu; Caifen Wang; Congcong Meng; Bo Hai; Shiqiang Zhu (DSC, 2019)

Automatic Breast Cancer Grading of Histological Images using Dilated Residual Network. - Yanyuet Man; Hailong Yao (ICBBT, 2019)

A Privacy-Preserving RLWE-Based Remote Biometric Authentication Scheme for Single and Multi-Server Environments. - Hailong Yao; Caifen Wang; Xingbing Fu; Chao Liu 039; Bin Wu 023; Fagen Li (IEEE Access, 2019)

Design Methodology for TFT-Based Pseudo-CMOS Logic Array With Multilayer Interconnection Architecture and Optimization Algorithms. - Qinghang Zhao; Wenyu Sun; Jiaqing Zhao; Jian Zhao 004; Hailong Yao; Tsung-Yi Ho; Xiaojun Guo; Huazhong Yang; Yongpan Liu (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019)

Transfer Learning-Based Microfluidic Design System for Concentration Generation∗. - Weiqing Ji; Tsung-Yi Ho; Hailong Yao (DAC, 2020)

TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. - Mingyang Kou; Jiangyuan Gu; Shaojun Wei; Hailong Yao; Shouyi Yin (DAC, 2020)

Leveled Adaptively Strong-Unforgeable Identity-Based Fully Homomorphic Signatures. - Caifen Wang; Bin Wu 023; Hailong Yao (IEEE Access, 2020)

Impersonation Attacks on Lightweight Anonymous Authenticated Key Exchange Scheme for IoT. - Hailong Yao; Caifen Wang; Xingbing Fu; Chao Liu 039; Bin Wu 023; Fagen Li (IACR Cryptol. ePrint Arch., 2020)

Microfluidic Design for Concentration Gradient Generation Using Artificial Neural Network. - Weiqing Ji; Tsung-Yi Ho; Junchao Wang; Hailong Yao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Lookup Table-Based Fast Reliability-Aware Sample Preparation Using Digital Microfluidic Biochips. - Lingxuan Shao; Wentai Li; Tsung-Yi Ho; Sudip Roy 001; Hailong Yao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Integrated Control-Fluidic Codesign Methodology for Paper-Based Digital Microfluidic Biochips. - Qin Wang 005; Ulf Schlichtmann; Yici Cai; Weiqing Ji; Zeyan Li; Haena Cheong; Oh-Sun Kwon; Hailong Yao; Tsung-Yi Ho; Kwanwoo Shin; Bing Li 005 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

URBER: Ultrafast Rule-Based Escape Routing Method for Large-Scale Sample Delivery Biochips. - Jiayi Weng; Tsung-Yi Ho; Weiqing Ji; Peng Liu; Mengdi Bao; Hailong Yao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Multicontrol: Advanced Control-Logic Synthesis for Flow-Based Microfluidic Biochips. - Ying Zhu 008; Xing Huang 001; Bing Li 005; Tsung-Yi Ho; Qin Wang 005; Hailong Yao; Robert Wille; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)

Machine Learning Based Acceleration Method for Ordered Escape Routing. - Zhiyang Chen 006; Weiqing Ji; Yihao Peng; Datao Chen; Mingyu Liu; Hailong Yao (ACM Great Lakes Symposium on VLSI, 2021)

Concentration Gradients Enhancement of Christmas-Tree Structure Based on a Look-Up Table. - Wei Zhang 012; Yongxiao Zhou; Tsung-Yi Ho; Hailong Yao (ACM Great Lakes Symposium on VLSI, 2021)

A certificateless linearly homomorphic signature scheme for network coding and its application in the IoT. - Bin Wu 023; Caifen Wang; Hailong Yao (Peer-to-Peer Netw. Appl., 2021)

Splitter-Aware Multiterminal Routing With Length-Matching Constraint for RSFQ Circuits. - Mingyang Kou; Pei-Yi Cheng; Jun Zeng 001; Tsung-Yi Ho; Kazuyoshi Takagi; Hailong Yao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

DCSA: Distributed Channel-Storage Architecture for Flow-Based Microfluidic Biochips. - Chunfeng Liu; Xing Huang 001; Bing Li 005; Hailong Yao; Paul Pop; Tsung-Yi Ho; Ulf Schlichtmann (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021)

GNN-based concentration prediction for random microfluidic mixers. - Weiqing Ji; Xingzhuo Guo; Shouan Pan; Tsung-Yi Ho; Ulf Schlichtmann; Hailong Yao (DAC, 2022)

GEML: GNN-based efficient mapping method for large loop applications on CGRA. - Mingyang Kou; Jun Zeng; Boxiao Han; Fei Xu; Jiangyuan Gu; Hailong Yao (DAC, 2022)

KunlunTVM: A Compilation Framework for Kunlun Chip Supporting Both Training and Inference. - Jun Zeng; Mingyang Kou; Hailong Yao (ACM Great Lakes Symposium on VLSI, 2022)

A Semi-supervised Framework for Automatic Pixel-Wise Breast Cancer Grading of Histological Images. - Kenglun Chang; Yanyuet Man; Hailong Yao (MICAD, 2022)

NeuroSchedule: A Novel Effective GNN-based Scheduling Method for High-level Synthesis. - Jun Zeng; Mingyang Kou; Hailong Yao (NeurIPS, 2022)

ECC-based lightweight authentication and access control scheme for IoT E-healthcare. - Hailong Yao; Qiao Yan; Xingbing Fu; Zhibin Zhang; Caihui Lan (Soft Comput., 2022)

Contamination-Aware Synthesis for Programmable Microfluidic Devices. - Hui-Chieh Yu; Yu-Huei Lin; Zhiyang Chen 006; Bing Li 005; Xing Huang 001; Ulf Schlichtmann; Tsung-Yi Ho; Hailong Yao (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022)

A Compilation Toolchain of Neural Networks for FPGA Backend. - Jun Zeng; Panfeng Wang; Haili Wang; Hailong Yao; Fuchun Sun (ASICON, 2023)

GAT-based Concentration Prediction for Random Microfluidic Mixers with Multiple Input Flow Rates. - Weiqing Ji; Hailong Yao; Tsung-Yi Ho; Ulf Schlichtmann; Xia Yin (ACM Great Lakes Symposium on VLSI, 2023)

SOAER: Self-Obstacle Avoiding Escape Routing for Paper-Based Digital Microfluidic Biochips. - Weiqing Ji; Xingcheng Yao; Hailong Yao; Tsung-Yi Ho; Ulf Schlichtmann; Xia Yin (ACM Great Lakes Symposium on VLSI, 2023)

NeuroEscape: Ordered Escape Routing via Monte-Carlo Tree Search and Neural Network. - Zhiyang Chen 006; Tsung-Yi Ho; Ulf Schlichtmann; Datao Chen; Mingyu Liu; Hailong Yao; Xia Yin (ICCAD, 2023)

TAEM 2.0: A Faster Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRA. - Mingyang Kou; Jiangyuan Gu; Hailong Yao; Shaojun Wei; Shouyi Yin (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

A Cooperative Multiagent Reinforcement Learning Framework for Droplet Routing in Digital Microfluidic Biochips. - Chen Jiang; Rongquan Yang; Qi Xu; Hailong Yao; Tsung-Yi Ho; Bo Yuan 006 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023)

Supervised Contrastive Learning based Fine-tuning Framework with Small-Scale WSI Dataset on ViT. - Kenglun Chang; Jintian Ge; Hailong Yao; Yin Xia (ICBBT, 2024)

Mr.TPL: A Method for Multi-Pin Net Router in Triple Patterning Lithography. - Chengkai Wang; Weiqing Ji; Mingyang Kou; Zhiyang Chen 006; Fei Li; Hailong Yao (CoRR, 2024)

KASE-AKA: Key-aggregate keyword searchable encryption against keyword guessing attack and authorization abuse. - Caihui Lan; Haifeng Li 009; Caifen Wang; Xiaodong Yang 006; Hailong Yao (Comput. Stand. Interfaces, 2024)

GNN-Based Concentration Prediction With Variable Input Flow Rates for Microfluidic Mixers. - Weiqing Ji; Xingzhuo Guo; Shouan Pan; Fei Long; Tsung-Yi Ho; Ulf Schlichtmann; Hailong Yao (IEEE Trans. Biomed. Circuits Syst., 2024)

VAER: Via-Aware Escape Routing for Chiplet Interconnection. - Haochang Tian; Weiqing Ji; Mingyang Kou; Chengkai Wang; Fei Li; Hailong Yao (ACM Great Lakes Symposium on VLSI, 2025)

Coal mine underground target search based on markov transition field and hill diversity. - Jiaojuan Wang; Hailong Yao; Minghan Guo; Tongyang Dao; Hongbin Dou; Xuefeng Zhu (Signal Image Video Process., 2025)