9.6 A 2.7-to-4.3GHz, 0.16psrms-jitter, -246.8dB-FOM, digital fractional-N sampling PLL in 28nm CMOS. - Xiang Gao; Olivier Burg; Haisong Wang; Wanghua Wu; Cao-Thong Tu; Konstantinos Manetakis; Fan Zhang; Luns Tee; Mustafa Yayla; Sining Xiang; Randy Tsang; Li Lin 009 (ISSCC, 2016)

9.4 A 2×2 WLAN and Bluetooth combo SoC in 28nm CMOS with on-chip WLAN digital power amplifier, integrated 2G/BT SP3T switch and BT pulling cancelation. - Renaldi Winoto; Ashkan Olyaei; Mohammad Hajirostam; Wai Lau; Xiang Gao; Arnab Mitra 002; Ovidiu Carnu; Philip Godoy; Luns Tee; Hao Li; Erdem Erdogan; Alden Wong; et al. (ISSCC, 2016)