Design considerations for 2nd-order and 3rd-order bang-bang CDR loops. - Shoujun Wang; Haitao Mei 002; Mashkoor Baig; William Bereza; Tadeusz Kwasniewski; Rakesh H. Patel (CICC, 2005)

8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2. - Marc-Andre LaCroix; Euhan Chong; Weilun Shen; Ehud Nir; Faisal Ahmed Musa; Haitao Mei 002; Mohammad-Mahdi Mohsenpour; Semyon Lebedev; Babak Zamanlooy; Carlos Carvalho; Qian Xin; Dmitry Petrov; et al. (ISSCC, 2021)