Validating GCSE in the scheduling of high-level synthesis. - Jian Hu; Yongyang Hu; Long Yu; Haitao Yang 006; Yun Kang; Jie Cheng (ATS, 2020)

Formal Verification of GCSE in the Scheduling of High-level Synthesis: Work-in-Progress. - Jian Hu; Yongyang Hu; Long Yu; Wentao Wang; Haitao Yang 006; Yun Kang; Jie Cheng (CODES+ISSS, 2020)

Multi-thread Simulation-based Equivalence Checking between SIM and RTI. - Jian Hu; Yongyang Hu; Guanwu Wang; Guilin Chen; Haitao Yang 006; Yun Kang; Kang Wang (CSAE, 2020)

DssEC: A Deep State Sequence Based Equivalence Checker. - Jian Hu; Yun Kang; Yongyang Hu; Haitao Yang 006; Le Tong; Jie Cheng; Junquan Deng (CSAE, 2021)

A Path-Based Equivalence Checking Method Between System Level and RTL Descriptions Using Machine Learning. - Jian Hu; Yongyang Hu; Qi Lv; Wentao Wang; Guanwu Wang; Guilin Chen; Kang Wang; Yun Kang; Haitao Yang 006 (J. Circuits Syst. Comput., 2021)

A Hybrid Method for Equivalence Checking Between System Level and RTL. - Jian Hu; Minhui Hu; Kuang Zhao; Yun Kang; Haitao Yang 006; Jie Cheng (J. Circuits Syst. Comput., 2022)