Acceleration Techniques for Chip-Multiprocessor Simulator Debug. - Haixia Wang 001; Dongsheng Wang 002; Peng Li 031 (Asia-Pacific Computer Systems Architecture Conference, 2006)

SRC-based Cache Coherence Protocol in Chip Multiprocessor. - Haixia Wang 001; Dongsheng Wang 002; Peng Li 031 (FCST, 2006)

LIRAC: Using Live Range Information to Optimize Memory Access. - Peng Li 031; Dongsheng Wang 002; Haixia Wang 001; Meijuan Lu; Weimin Zheng (ARCS, 2007)

Exploit Temporal Locality of Shared Data in SRC Enabled CMP. - Haixia Wang 001; Dongsheng Wang 002; Peng Li 031; Jinglei Wang; XianPing Fu (NPC, 2007)

An Efficient Lightweight Shared Cache Design for Chip Multiprocessors. - Jinglei Wang; Dongsheng Wang 002; Yibo Xue; Haixia Wang 001 (APPT, 2009)

A Novel Cache Organization for Tiled Chip Multiprocessor. - Xi Zhang 008; Dongsheng Wang 002; Yibo Xue; Haixia Wang 001; Jinglei Wang (APPT, 2009)

Network caching for Chip Multiprocessors. - Jinglei Wang; Yibo Xue; Haixia Wang 001; Dongsheng Wang 002 (IPCCC, 2009)

Fast Hierarchical Cache Directory: A Scalable Cache Organization for Large-Scale CMP. - Chongmin Li; Haixia Wang 001; Yibo Xue; Xi Zhang 008; Dongsheng Wang 002 (NAS, 2010)

A Cache Replacement Policy Using Adaptive Insertion and Re-reference Prediction. - Xi Zhang 008; Chongmin Li; Haixia Wang 001; Dongsheng Wang 002 (SBAC-PAD, 2010)

Hierarchical Cache Directory for CMP. - Songliu Guo; Hai-Xia Wang 001; Yibo Xue; Chong-Min Li; Dong-Sheng Wang 002 (J. Comput. Sci. Technol., 2010)

CCNoC: Cache-Coherent Network on Chip for Chip Multiprocessors. - Jinglei Wang; Yibo Xue; Hai-Xia Wang 001; Chong-Min Li; Dong-Sheng Wang 002 (J. Comput. Sci. Technol., 2010)

Scalable Proximity-Aware Cache Replication in Chip Multiprocessors. - Chongmin Li; Haixia Wang 001; Yibo Xue; Dongsheng Wang 002; Jian Li 059 (PACT, 2011)

Enhanced Adaptive Insertion Policy for Shared Caches. - Chongmin Li; Dongsheng Wang 002; Yibo Xue; Haixia Wang 001; Xi Zhang 008 (APPT, 2011)

A Read-Write Aware Replacement Policy for Phase Change Memory. - Xi Zhang 008; Qian Hu; Dongsheng Wang 002; Chongmin Li; Haixia Wang 001 (APPT, 2011)

High performance cache block replication using re-reference probability in CMPs. - Jinglei Wang; Dongsheng Wang 002; Haixia Wang 001; Yibo Xue (HiPC, 2011)

Coherent Temporal Streams in PARSEC. - Muhammad Abid Mughal; Haixia Wang 001; Dongsheng Wang 002 (NAS, 2011)

A Novel Cache Replacement Policy via Dynamic Adaptive Insertion and Re-Reference Prediction. - Xi Zhang 008; Chongmin Li; Zhenyu Liu 001; Haixia Wang 001; Dongsheng Wang 002; Takeshi Ikenaga (IEICE Trans. Electron., 2011)

Proximity-Aware cache Replication. - Chongmin Li; Dongsheng Wang 002; Haixia Wang 001; Yibo Xue; Jian Li 059 (ASP-DAC, 2012)

Dynamic reusability-based replication with network address mapping in CMPs. - Jinglei Wang; Dongsheng Wang 002; Haixia Wang 001; Yibo Xue (ASP-DAC, 2012)

Wear-Resistant Hybrid Cache Architecture with Phase Change Memory. - Sanchuan Guo; Zhenyu Liu 001; Dongsheng Wang 002; Haixia Wang 001; Guohong Li (NAS, 2012)

Data Access Type Aware Replacement Policy for Cache Clustering Organization of Chip Multiprocessors. - Chongmin Li; Dongsheng Wang 002; Haixia Wang 001; Guohong Li; Yibo Xue (APPT, 2013)

Security Memory System for Mobile Device or Computer Against Memory Attacks. - Genxian Liu; Xi Zhang 008; Dongsheng Wang 002; Zhenyu Liu 001; Haixia Wang 001 (ISCTCS, 2013)

The Case of Using Multiple Streams in Streaming. - Muhammad Abid Mughal; Hai-Xia Wang 001; Dong-Sheng Wang 002 (Int. J. Autom. Comput., 2013)

Parallelizing Convolutional Neural Networks on Intel $$^{ textregistered }$$ Many Integrated Core Architecture. - Junjie Liu; Haixia Wang 001; Dongsheng Wang 002; Yuan Gao; Zuofeng Li (ARCS, 2015)

Pull-off buffer: Borrowing cache space to avoid deadlock for fault-tolerant NoC routing. - Airan Shao; Dongsheng Wang 002; Haixia Wang 001 (ICCD, 2016)

MAC: a novel systematically multilevel cache replacement policy for PCM memory. - Shenchen Ruan; Haixia Wang 001; Dongsheng Wang 002 (CoRR, 2016)

GDCRT: In-Memory 2D Geographical Dynamic Cascading Range Tree. - Yinxing Hou; Haixia Wang 001; Dongsheng Wang 002 (APPT, 2017)

FEBRE: A Fast and Efficient Bit-Flipping Reduction Technique to Extend PCM lifetime. - Peng Gao; Dongsheng Wang 002; Haixia Wang 001 (CANDAR, 2017)

Data-centric computation mode for convolution in deep neural networks. - Peiqi Wang 001; Zhenyu Liu 001; Haixia Wang 001; Dongsheng Wang 002 (IJCNN, 2017)

Cache Friendly Parallelization of Neural Encoder-Decoder Models Without Padding on Multi-core Architecture. - Yuchen Qiao; Kazuma Hashimoto; Akiko Eriguchi; Haixia Wang 001; Dongsheng Wang 002; Yoshimasa Tsuruoka; Kenjiro Taura (IPDPS Workshops, 2017)

Fast Recovery Techniques for Erasure-coded Clusters in Non-uniform Traffic Network. - Yunren Bai; Zihan Xu; Haixia Wang 001; Dongsheng Wang 002 (ICPP, 2019)

CRaft: An Erasure-coding-supported Version of Raft for Reducing Storage Cost and Network Cost. - Zizhong Wang; Tongliang Li; Haixia Wang 001; Airan Shao; Yunren Bai; Shangming Cai; Zihan Xu; Dongsheng Wang 002 (FAST, 2020)

CARD: A Congestion-Aware Request Dispatching Scheme for Replicated Metadata Server Cluster. - Shangming Cai; Dongsheng Wang 002; Zhanye Wang; Haixia Wang 001 (ICPP, 2020)

An Adaptive Erasure-Coded Storage Scheme with an Efficient Code-Switching Algorithm. - Zizhong Wang; Haixia Wang 001; Airan Shao; Dongsheng Wang 002 (ICPP, 2020)

Parallelizing and optimizing neural Encoder-Decoder models without padding on multi-core architecture. - Yuchen Qiao; Kazuma Hashimoto; Akiko Eriguchi; Haixia Wang 001; Dongsheng Wang 002; Yoshimasa Tsuruoka; Kenjiro Taura (Future Gener. Comput. Syst., 2020)

CacheGuard: A Behavior Model Checker for Cache Timing Side-Channel Security: (Invited Paper). - Zihan Xu; Lingfeng Yin; Yongqiang Lyu 001; Haixia Wang 001; Gang Qu 001; Dongsheng Wang 002 (ASP-DAC, 2022)

Model Checking for Microarchitectural Data Sampling Security. - Qian Ke; Chunlu Wang; Haixia Wang 001; Yongqiang Lyu 001; Zihan Xu; Dongsheng Wang 002 (DSC, 2022)

SSB-Tree: Making Persistent Memory B+- Trees Crash-Consistent and Concurrent by Lazy-Box. - Tongliang Li; Haixia Wang 001; Airan Shao; Dongsheng Wang 002 (IPDPS, 2022)

PMUSpill: The Counters in Performance Monitor Unit that Leak SGX-Protected Secrets. - Pengfei Qiu; Yongqiang Lyu 001; Haixia Wang 001; Dongsheng Wang 002; Chang Liu 117; Qiang Gao; Chunlu Wang; Rihui Sun; Gang Qu 001 (CoRR, 2022)

DynaComm: Accelerating Distributed CNN Training Between Edges and Clouds Through Dynamic Communication Scheduling. - Shangming Cai; Dongsheng Wang 002; Haixia Wang 001; Yongqiang Lyu 001; Guangquan Xu; Xi Zheng 001; Athanasios V. Vasilakos (IEEE J. Sel. Areas Commun., 2022)

Leaky MDU: ARM Memory Disambiguation Unit Uncovered and Vulnerabilities Exposed. - Chang Liu 117; Yongqiang Lyu 001; Haixia Wang 001; Pengfei Qiu; Dapeng Ju; Gang Qu 001; Dongsheng Wang 002 (DAC, 2023)

SCAFinder: Formal Verification of Cache Fine-Grained Features for Side Channel Detection. - Shixuan Zhang; Haixia Wang 001; Pengfei Qiu; Yongqiang Lyu 001; Hongpeng Wang; Dongsheng Wang 002 (IEEE Trans. Inf. Forensics Secur., 2024)

Lightning: Leveraging DVFS-induced Transient Fault Injection to Attack Deep Learning Accelerator of GPUs. - Rihui Sun; Pengfei Qiu; Yongqiang Lyu 001; Jian Dong; Haixia Wang 001; Dongsheng Wang 002; Gang Qu 001 (ACM Trans. Design Autom. Electr. Syst., 2024)