Implementation of a baseline RISC for the realization of a dynamically reconfigurable processor. - Hajer Najjar; Riad Bourguiba; Jaouhar Mounie (SSD, 2015)

A new programmable ALU architecture for hard-core processor. - Hajer Najjar; Riad Bourguiba; Jaouhar Mouine (SSD, 2016)

A Reusable Hybrid RISC Processor with Programmable Instruction Set. - Hajer Najjar; Riad Bourguiba; Jaouhar Mouine (SSD, 2018)