Reinforcement Learning by Stochastic Hill Climbing on Discounted Reward. - Hajime Kimura; Masayuki Yamamura; Shigenobu Kobayashi (ICML, 1995)

Reinforcement Learning in POMDPs with Function Approximation. - Hajime Kimura; Kazuteru Miyazaki; Shigenobu Kobayashi (ICML, 1997)

An Analysis of Actor/Critic Algorithms Using Eligibility Traces: Reinforcement Learning with Imperfect Value Function. - Hajime Kimura; Shigenobu Kobayashi (ICML, 1998)

Power plant start-up scheduling: a reinforcement learning approach combined with evolutionary computation. - Akimoto Kamiya; Hajime Kimura; Masayuki Yamamura; Shigenobu Kobayashi (J. Intell. Fuzzy Syst., 1998)

Efficient Non-Linear Control by Combining Q-learning with Local Linear Controllers. - Hajime Kimura; Shigenobu Kobayashi (ICML, 1999)

A Universal Generalization for Temporal-Difference Learning Using Haar Basis Functions. - Susumu Katayama; Hajime Kimura; Shigenobu Kobayashi (ICML, 2000)

Reinforcement learning of walking behavior for a four-legged robot. - Hajime Kimura; Toru Yamashita; Shigenobu Kobayashi (CDC, 2001)

A computational model of cerebellum and midbrain to realize the human smooth constrained motion and bimanual cooperative motion. - Takayuki Nakayama; Hajime Kimura (CDC, 2001)

Moving target detection from infrared images using genetic algorithms. - Minoru Kikuchi; Hajime Kimura; Shigenobu Kobayashi (Syst. Comput. Jpn., 2003)

Multi-objective genetic algorithms for pipe arrangement design. - Satoshi Ikehira; Hajime Kimura (GECCO, 2006)

A unified motion planning method for a multifunctional underwater robot. - Koichiro Shiraishi; Hajime Kimura (Artif. Life Robotics, 2009)

1Mbit 1T1C 3D DRAM with Monolithically Stacked One Planar FET and Two Vertical FET Heterogeneous Oxide Semiconductor layers over Si CMOS. - Yuki Okamoto; Yusuke Komura; Toshiki Mizuguchi; Toshihiko Saito; Minato Ito; K. Kimura; Tatsuya Onuki; Yoshinori Ando; Hiromi Sawai; Tsutomu Murakawa; Hitoshi Kunitake; Takanori Matsuzaki; et al. (VLSI Technology and Circuits, 2023)

Heterogeneous Oxide Semiconductor FETs Comprising Planar FET and Vertical Channel FETs Monolithically Stacked on Si CMOS, Enabling 1-Mbit 3D DRAM. - Hiraki Inoue; Takeya Hirose; Toshiki Mizuguchi; Yusuke Komura; Toshihiko Saito; Minato Ito; Kiyotaka Kimura; Tatsuya Onuki; Yoshinori Ando; Hiromi Sawai; Tsutomu Murakawa; Hitoshi Kunitake; et al. (IMW, 2024)