A 64-bit floating-point processing unit with a horizontal instruction code for parallel operations. - Akira Katsuno; Hiromasa Takahashi; Hajime Kubosawa; Tomio Sato; Atsuhiro Suga; Gensuke Goto (ICCD, 1990)

A 1.2-W, 2.16-GOPS/720-MFLOPS embedded superscalar microprocessor for multimedia applications. - Hajime Kubosawa; Hiromasa Takahashi; Satoshi Ando; Yoshimi Asada; Akira Asato; Atsuhiro Suga; Michihide Kimura; Naoshi Higaki; Hideo Miyake; Tomio Sato; Hideaki Anbutsu; Toshitaka Tsuda; et al. (IEEE J. Solid State Circuits, 1998)

A 2.5-GFLOPS, 6.5 million polygons per second, four-way VLIW geometry processor with SIMD instructions and a software bypass mechanism. - Hajime Kubosawa; Naoshi Higaki; Satoshi Ando; Hiromasa Takahashi; Yoshimi Asada; Hideaki Anbutsu; Tomio Sato; Masato Sakate; Atsuhiro Suga; Michihide Kimura; Hideo Miyake; Hiroshi Okano; et al. (IEEE J. Solid State Circuits, 1999)