Exploiting Spatial Store Locality Through Permission Caching in Software DSMs. - Håkan Zeffer; Zoran Radovic; Oskar Grenholm; Erik Hagersten (Euro-Par, 2004)

VASA: A Simulator Infrastructure with Adjustable Fidelity. - Dan Wallin; Håkan Zeffer; Martin Karlsson; Erik Hagersten (IASTED PDCS, 2005)

TMA: a trap-based memory architecture. - Håkan Zeffer; Zoran Radovic; Martin Karlsson; Erik Hagersten (ICS, 2006)

Modeling Cache Sharing on Chip Multiprocessor Architectures. - Pavlos Petoumenos; Georgios Keramidas; Håkan Zeffer; Stefanos Kaxiras; Erik Hagersten (IISWC, 2006)

Exploiting locality: a flexible DSM approach. - Håkan Zeffer; Zoran Radovic; Erik Hagersten (IPDPS, 2006)

A statistical multiprocessor cache model. - Erik Berg; Håkan Zeffer; Erik Hagersten (ISPASS, 2006)

Towards Low-Complexity Scalable Shared-Memory Architectures. - Håkan Zeffer (2006)

A case for low-complexity MP architectures. - Håkan Zeffer; Erik Hagersten (SC, 2007)

Simultaneous speculative threading: a novel pipeline architecture implemented in sun's rock processor. - Shailender Chaudhry; Robert Cypher; Magnus Ekman; Martin Karlsson; Anders Landin; Sherman Yip; Håkan Zeffer; Marc Tremblay (ISCA, 2009)

Rock: A High-Performance Sparc CMT Processor. - Shailender Chaudhry; Robert Cypher; Magnus Ekman; Martin Karlsson; Anders Landin; Sherman Yip; Håkan Zeffer; Marc Tremblay (IEEE Micro, 2009)