Temporal performance degradation under NBTI: estimation and design for improved reliability of nanoscale circuits. - Bipul Chandra Paul; Kunhyuk Kang; Haldun Kufluoglu; Muhammad Ashraful Alam; Kaushik Roy 001 (DATE, 2006)

Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI. - Kunhyuk Kang; Haldun Kufluoglu; Muhammad Ashraful Alam; Kaushik Roy 001 (ICCD, 2006)

A comprehensive model for PMOS NBTI degradation: Recent progress. - Muhammad Ashraful Alam; Haldun Kufluoglu; Dhanoop Varghese; S. Mahapatra (Microelectron. Reliab., 2007)

Impact of Negative-Bias Temperature Instability in Nanoscale SRAM Array: Modeling and Analysis. - Kunhyuk Kang; Haldun Kufluoglu; Kaushik Roy 001; Muhammad Ashraful Alam (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Negative Bias Temperature Instability: Estimation and Design for Improved Reliability of Nanoscale Circuits. - Bipul Chandra Paul; Kunhyuk Kang; Haldun Kufluoglu; Muhammad Ashraful Alam; Kaushik Roy 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Recovery modeling of negative bias temperature instability (NBTI) for SPICE-compatible circuit aging simulators. - Haldun Küflüoglu; Cathy Chancellor; Min Chen 024; Claude Cirba; Vijay Reddy (ACM J. Emerg. Technol. Comput. Syst., 2014)