Power-smart system-on-chip architecture for embedded cryptosystems. - Radu Muresan; Haleh Vahedi; Y. Zhanrong; Stefano Gregori (CODES+ISSS, 2005)

An integrated current flattening module for embedded cryptosystems. - Xuequn Li; Haleh Vahedi; Radu Muresan; Stefano Gregori (ISCAS (1), 2005)

On-chip current flattening circuit with dynamic voltage scaling. - Haleh Vahedi; Radu Muresan; Stefano Gregori (ISCAS, 2006)

On-Chip Power-Efficient Current Flattening Circuit. - Haleh Vahedi; Stefano Gregori; Radu Muresan (J. Circuits Syst. Comput., 2009)

The effectiveness of a current flattening circuit as countermeasure against DPA attacks. - Haleh Vahedi; Stefano Gregori; Radu Muresan (Microelectron. J., 2011)

11.2 A 26.5625-to-106.25Gb/s XSR SerDes with 1.55pJ/b Efficiency in 7nm CMOS. - Ravi Shivnaraine; Marcus van Ierssel; Kamran Farzan; Dominic DiClemente; George Ng; Nanyan Wang; Javid Musayev; Gairik Dutta; Masumi Shibata; Arash Moradi; Haleh Vahedi; Manavi Farzad; et al. (ISSCC, 2021)