Architecture-Level Design Space Exploration of Super Scalar Microarchitecture for Network Applications. - Mostafa E. Salehi; Hamed Dorosti; Sied Mehdi Fakhraie (DSD, 2010)

Dynamic Soft Error Hardening via Joint Body Biasing and Dynamic Voltage Scaling. - Farshad Firouzi; Amir Yazdanbakhsh; Hamed Dorosti; Sied Mehdi Fakhraie (DSD, 2011)

Process variation-aware approximation for efficient timing management of digital circuits. - Mohsen Faryabi; Hamed Dorosti; Mehdi Modarressi; Sied Mehdi Fakhraie (EWDTS, 2015)

Ultralow-Energy Variation-Aware Design: Adder Architecture Study. - Hamed Dorosti; Ali Teymouri; Sied Mehdi Fakhraie; Mostafa E. Salehi (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Lifetime improvement by exploiting aggressive voltage scaling during runtime of error-resilient applications. - Farzaneh Nakhaee; Mehdi Kamal; Ali Afzali-Kusha; Massoud Pedram; Sied Mehdi Fakhraie; Hamed Dorosti (Integr., 2018)