Designing Area and Performance Constrained SIMD/VLIW Image Processing Architectures. - Hamed Fatemi; Henk Corporaal; Twan Basten; Richard P. Kleihorst; Pieter P. Jonker (ACIVS, 2005)

Dynamic-SIMD for lens distortion compensation. - Bart Mesman; Hamed Fatemi; Henk Corporaal; Twan Basten (ASAP, 2006)

Run-time reconfiguration of communication in SIMD architectures. - Hamed Fatemi; Bart Mesman; Henk Corporaal; Twan Basten; Pieter P. Jonker (IPDPS, 2006)

RC-SIMD: Reconfigurable communication SIMD architecture for image processing applications. - Hamed Fatemi; Bart Mesman; Henk Corporaal; Twan Basten; Richard P. Kleihorst (J. Embed. Comput., 2006)

DC-SIMD : Dynamic communication for SIMD processors. - Raymond Frijns; Hamed Fatemi; Bart Mesman; Henk Corporaal (IPDPS, 2008)

Sliding-Mode Control to Compensate PVT Variations in dual core systems. - Hamid Reza Pourshaghaghi; Hamed Fatemi; José Pineda de Gyvez (DATE, 2012)

Digital Systems Power Management for High Performance Mixed Signal Platforms. - Ajay Kapoor; Cas Groot; Gerard Villar Pique; Hamed Fatemi; Juan Diego Echeverri; Leo Sevat; Maarten Vertregt; Maurice Meijer; Vibhu Sharma; Yu Pu; José Pineda de Gyvez (IEEE Trans. Circuits Syst. I Regul. Pap., 2014)

Reducing energy consumption in microcontroller-based platforms with low design margin co-processors. - Andres Gomez 001; Christian Pinto; Andrea Bartolini; Davide Rossi; Luca Benini; Hamed Fatemi; José Pineda de Gyvez (DATE, 2015)

Supervised learning based model for predicting variability-induced timing errors. - Xun Jiao; Abbas Rahimi; Balakrishnan Narayanaswamy; Hamed Fatemi; José Pineda de Gyvez; Rajesh K. Gupta 001 (NEWCAS, 2015)

Lower power by voltage stacking: a fine-grained system design approach. - Kristof Blutman; Ajay Kapoor; Jacinto Garcia Martinez; Hamed Fatemi; José Pineda de Gyvez (DAC, 2016)

Circuit valorization in the IC design ecosystem. - José Pineda de Gyvez; Hamed Fatemi; Maarten Vertregt (ICCAD, 2016)

A microcontroller with 96% power-conversion efficiency using stacked voltage domains. - Kristof Blutman; Ajay Kapoor; Arjun Majumdar; Jacinto Garcia Martinez; Juan Diego Echeverri; Leo Sevat; Arnoud P. van der Wel; Hamed Fatemi; José Pineda de Gyvez; Kofi A. A. Makinwa (VLSI Circuits, 2016)

Floorplan and placement methodology for improved energy reduction in stacked power-domain design. - Kristof Blutman; Hamed Fatemi; Andrew B. Kahng; Ajay Kapoor; Jiajia Li 002; José Pineda de Gyvez (ASP-DAC, 2017)

A scan-chain based state retention methodology for IoT processors operating on intermittent energy. - Pascal Alexander Hager; Hamed Fatemi; José Pineda de Gyvez; Luca Benini (DATE, 2017)

A Low-Power Microcontroller in a 40-nm CMOS Using Charge Recycling. - Kristof Blutman; Ajay Kapoor; Arjun Majumdar; Jacinto Garcia Martinez; Juan Diego Echeverri; Leo Sevat; Arnoud P. van der Wel; Hamed Fatemi; Kofi A. A. Makinwa; José Pineda de Gyvez (IEEE J. Solid State Circuits, 2017)

Increasing the energy efficiency of microcontroller platforms with low-design margin co-processors. - Andres Gomez 001; Andrea Bartolini; Davide Rossi; Baris Can Kara; Hamed Fatemi; José Pineda de Gyvez; Luca Benini (Microprocess. Microsystems, 2017)

Logic Design Partitioning for Stacked Power Domains. - Kristof Blutman; Hamed Fatemi; Ajay Kapoor; Andrew B. Kahng; Jiajia Li 002; José Pineda de Gyvez (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Effective In-Situ Chip Health Monitoring with Selective Monitor Insertion Along Timing Paths. - Hadi Ahmadi Balef; Hamed Fatemi; Kees Goossens; José Pineda de Gyvez (ACM Great Lakes Symposium on VLSI, 2018)

Low power latch based design with smart retiming. - Kamlesh Singh; Hailong Jiao; Jos Huisken; Hamed Fatemi; José Pineda de Gyvez (ISQED, 2018)

Torpor: A Power-Aware HW Scheduler for Energy Harvesting IoT SoCs. - P. Anagnostou; Andres Gomez 001; Pascal A. Hager; Hamed Fatemi; José Pineda de Gyvez; Lothar Thiele; Luca Benini (PATMOS, 2018)

CLIM: A Cross-Level Workload-Aware Timing Error Prediction Model for Functional Units. - Xun Jiao; Abbas Rahimi; Yu Jiang 001; Jianguo Wang 001; Hamed Fatemi; José Pineda de Gyvez; Rajesh K. Gupta 001 (IEEE Trans. Computers, 2018)

Keyword Spotting using Time-Domain Features in a Temporal Convolutional Network. - Emad A. Ibrahim; Jos Huisken; Hamed Fatemi; José Pineda de Gyvez (DSD, 2019)

Energy and power awareness in hardware schedulers for energy harvesting IoT SoCs. - P. Anagnostou; Andres Gomez 001; Pascal A. Hager; Hamed Fatemi; José Pineda de Gyvez; Lothar Thiele; Luca Benini (Integr., 2019)

Enhancing sensitivity-based power reduction for an industry IC design context. - Hamed Fatemi; Andrew B. Kahng; Hyein Lee 001; Jiajia Li 002; José Pineda de Gyvez (Integr., 2019)

Timing Speculation With Optimal In Situ Monitoring Placement and Within-Cycle Error Prevention. - Hadi Ahmadi Balef; Hamed Fatemi; Kees Goossens; José Pineda de Gyvez (IEEE Trans. Very Large Scale Integr. Syst., 2019)

Optimal bounded-skew steiner trees to minimize maximum k-active dynamic power. - Hamed Fatemi; Andrew B. Kahng; Minsoo Kim; José Pineda de Gyvez (SLIP, 2020)

Heuristic Methods for Fine-Grain Exploitation of FDSOI. - Hamed Fatemi; Andrew B. Kahng; Hyein Lee 001; José Pineda de Gyvez (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020)