Efficient power clock generation for adiabatic logic. - Hamid Mahmoodi-Meimand; Ali Afzali-Kusha (ISCAS (4), 2001)

High performance and low power FIR filter design based on sharing multiplication. - Jongsun Park 001; Woopyo Jeong; Hunsoo Choo; Hamid Mahmoodi-Meimand; Yongtao Wang; Kaushik Roy 001 (ISLPED, 2002)

Leakage Current in Deep-Submicron CMOS Circuits. - Kaushik Roy 001; Saibal Mukhopadhyay; Hamid Mahmoodi-Meimand (J. Circuits Syst. Comput., 2002)

Energy recovery clocking scheme and flip-flops for ultra low-energy applications. - Matthew Cooke; Hamid Mahmoodi-Meimand; Kaushik Roy 001 (ISLPED, 2003)

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits. - Kauschick Roy; Saibal Mukhopadhyay; Hamid Mahmoodi-Meimand (Proc. IEEE, 2003)

Estimation of delay variations due to random-dopant fluctuations in nano-scaled CMOS circuits. - Hamid Mahmoodi-Meimand; Saibal Mukhopadhyay; Kaushik Roy 001 (CICC, 2004)

First Level Hold: A Novel Low-Overhead Delay Fault Testing Technique. - Swarup Bhunia; Hamid Mahmoodi-Meimand; Arijit Raychowdhury; Kaushik Roy 001 (DFT, 2004)

Hardware architecture and VLSI implementation of a low-power high-performance polyphase channelizer with applications to subband adaptive filtering. - Yongtao Wang; Hamid Mahmoodi; Lih-Yih Chiou; Hunsoo Choo; Jongsun Park 001; Woopyo Jeong; Kaushik Roy 001 (ICASSP (5), 2004)

Statistical design and optimization of SRAM cell for yield enhancement. - Saibal Mukhopadhyay; Hamid Mahmoodi-Meimand; Kaushik Roy 001 (ICCAD, 2004)

A Novel Low-Power Scan Design Technique Using Supply Gating. - Swarup Bhunia; Hamid Mahmoodi-Meimand; Saibal Mukhopadhyay; Debjyoti Ghosh; Kaushik Roy 001 (ICCD, 2004)

Dual-edge triggered level converting flip-flops. - Hamid Mahmoodi-Meimand; Kaushik Roy 001 (ISCAS (2), 2004)

Data-retention flip-flops for power-down applications. - Hamid Mahmoodi-Meimand; Kaushik Roy 001 (ISCAS (2), 2004)

Computation sharing programmable FIR filter for low-power and high-performance applications. - Jongsun Park 001; Woopyo Jeong; Hamid Mahmoodi-Meimand; Yongtao Wang; Hunsoo Choo; Kaushik Roy 001 (IEEE J. Solid State Circuits, 2004)

Diode-footed domino: a leakage-tolerant high fan-in dynamic circuit design style. - Hamid Mahmoodi-Meimand; Kaushik Roy 001 (IEEE Trans. Circuits Syst. I Regul. Pap., 2004)

Leakage Current Based Stabilization Scheme for Robust Sense-Amplifier Design for Yield Enhancement in Nano-scale SRAM. - Saibal Mukhopadhyay; Arijit Raychowdhury; Hamid Mahmoodi-Meimand; Kaushik Roy 001 (Asian Test Symposium, 2005)

A novel synthesis approach for active leakage power reduction using dynamic supply gating. - Swarup Bhunia; Nilanjan Banerjee; Qikai Chen; Hamid Mahmoodi-Meimand; Kaushik Roy 001 (DAC, 2005)

A Novel Low-overhead Delay Testing Technique for Arbitrary Two-Pattern Test Application. - Swarup Bhunia; Hamid Mahmoodi-Meimand; Arijit Raychowdhury; Kaushik Roy 001 (DATE, 2005)

Energy recovery clocked dynamic logic. - Matthew Cooke; Hamid Mahmoodi-Meimand; Qikai Chen; Kaushik Roy 001 (ACM Great Lakes Symposium on VLSI, 2005)

A high speed and leakage-tolerant domino logic for high fan-in gates. - Farshad Moradi; Hamid Mahmoodi-Meimand; Ali Peiravi (ACM Great Lakes Symposium on VLSI, 2005)

Process Variation Tolerant Online Current Monitor for Robust Systems. - Qikai Chen; Saibal Mukhopadhyay; Hamid Mahmoodi; Kaushik Roy 001 (IOLTS, 2005)

Pre-capturing static pulsed flip-flops. - Aliakbar Ghadiri; Hamid Mahmoodi-Meimand (ISCAS (3), 2005)

Power Reduction in Test-Per-Scan BIST with Supply Gating and Efficient Scan Partitioning. - Swarup Bhunia; Hamid Mahmoodi-Meimand; Debjyoti Ghosh; Kaushik Roy 001 (ISQED, 2005)

Design of High Performance Sense Amplifier Using Independent Gate Control in sub-50nm Double-Gate MOSFET. - Saibal Mukhopadhyay; Hamid Mahmoodi-Meimand; Kaushik Roy 001 (ISQED, 2005)

A leakage control system for thermal stability during burn-in test. - Mesut Meterelliyoz; Hamid Mahmoodi; Kaushik Roy 001 (ITC, 2005)

Reliable and self-repairing SRAM in nano-scale technologies using leakage and delay monitoring. - Saibal Mukhopadhyay; Kunhyuk Kang; Hamid Mahmoodi; Kaushik Roy 001 (ITC, 2005)

Dual-Edge Triggered Static Pulsed Flip-Flops. - Aliakbar Ghadiri; Hamid Mahmoodi-Meimand (VLSI Design, 2005)

Modeling and Testing of SRAM for New Failure Mechanisms Due to Process Variations in Nanoscale CMOS. - Qikai Chen; Hamid Mahmoodi-Meimand; Swarup Bhunia; Kaushik Roy 001 (VTS, 2005)

Estimation of delay variations due to random-dopant fluctuations in nanoscale CMOS circuits. - Hamid Mahmoodi; Saibal Mukhopadhyay; Kaushik Roy 001 (IEEE J. Solid State Circuits, 2005)

Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS. - Saibal Mukhopadhyay; Hamid Mahmoodi-Meimand; Kaushik Roy 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005)

A process-tolerant cache architecture for improved yield in nanoscale technologies. - Amit Agarwal 001; Bipul Chandra Paul; Hamid Mahmoodi-Meimand; Animesh Datta; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Low-power scan design using first-level supply gating. - Swarup Bhunia; Hamid Mahmoodi-Meimand; Debjyoti Ghosh; Saibal Mukhopadhyay; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations. - Qikai Chen; Hamid Mahmoodi-Meimand; Swarup Bhunia; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Low-overhead design of soft-error-tolerant scan flip-flops with enhanced-scan capability. - Ashish Goel; Swarup Bhunia; Hamid Mahmoodi-Meimand; Kaushik Roy 001 (ASP-DAC, 2006)

Low power synthesis of dynamic logic circuits using fine-grained clock gating. - Nilanjan Banerjee; Kaushik Roy 001; Hamid Mahmoodi-Meimand; Swarup Bhunia (DATE, 2006)

Robust Sense Amplifier Design under Random Dopant Fluctuations in Nano-Scale CMOS Technologies. - Joyce Yeung; Hamid Mahmoodi (SoCC, 2006)

Double-Gate SOI Devices for Low-Power and High-Performance Applications. - Kaushik Roy 001; Hamid Mahmoodi-Meimand; Saibal Mukhopadhyay; Hari Ananthan; Aditya Bansal; Tamer Cakici (VLSI Design, 2006)

Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis. - Nilanjan Banerjee; Arijit Raychowdhury; Kaushik Roy 001; Swarup Bhunia; Hamid Mahmoodi (IEEE Trans. Very Large Scale Integr. Syst., 2006)

A novel high-performance and robust sense amplifier using independent gate control in sub-50-nm double-gate MOSFET. - Saibal Mukhopadhyay; Hamid Mahmoodi-Meimand; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2006)

Low-overhead design technique for calibration of maximum frequency at multiple operating points. - Somnath Paul; Sivasubramaniam Krishnamurthy; Hamid Mahmoodi; Swarup Bhunia (ICCAD, 2007)

Clock Gating and Negative Edge Triggering for Energy Recovery Clock. - Vishwanadh Tirumalashetty; Hamid Mahmoodi (ISCAS, 2007)

A low-power SRAM using bit-line charge-recycling technique. - Keejong Kim; Hamid Mahmoodi; Kaushik Roy 001 (ISLPED, 2007)

Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS. - Rajani Kuchipudi; Hamid Mahmoodi (ISQED, 2007)

Design of a Process Variation Tolerant Self-Repairing SRAM for Yield Enhancement in Nanoscaled CMOS. - Saibal Mukhopadhyay; Keejong Kim; Hamid Mahmoodi; Kaushik Roy 001 (IEEE J. Solid State Circuits, 2007)

Modeling and Circuit Synthesis for Independently Controlled Double Gate FinFET Devices. - Animesh Datta; Ashish Goel; R. T. Cakici; Hamid Mahmoodi; Dheepa Lekshmanan; Kaushik Roy 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007)

Session 8 - Characterization and test methods for device variability in nanoscale technologies. - Hamid Mahmoodi; Jeanne Trinko Mechler (CICC, 2008)

65NM sub-threshold 11T-SRAM for ultra low voltage applications. - Farshad Moradi; Dag T. Wisland; Snorre Aunet; Hamid Mahmoodi; Tuan Vu Cao (SoCC, 2008)

Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique. - Swarup Bhunia; Hamid Mahmoodi; Arijit Raychowdhury; Kaushik Roy 001 (J. Electron. Test., 2008)

A Low-Power SRAM Using Bit-Line Charge-Recycling. - Keejong Kim; Hamid Mahmoodi; Kaushik Roy 001 (IEEE J. Solid State Circuits, 2008)

Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias. - Saibal Mukhopadhyay; Hamid Mahmoodi; Kaushik Roy 001 (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008)

Ultra Low Power Full Adder Topologies. - Farshad Moradi; Dag T. Wisland; Hamid Mahmoodi; Snorre Aunet; Tuan Vu Cao; Ali Peiravi (ISCAS, 2009)

New subthreshold concepts in 65nm CMOS technology. - Farshad Moradi; Dag T. Wisland; Hamid Mahmoodi; Ali Peiravi; Snorre Aunet; Tuan Vu Cao (ISQED, 2009)

Virtual Age: Enabling Technologies and Trends. - Hamid Mahmoodi; Ali A. Jalali 001 (ITNG, 2009)

Full-custom design project for digital VLSI and IC design courses using synopsys generic 90nm CMOS library. - Eli Lyons; Vish Ganti; Richard Goldman; Vazgen Melikyan; Hamid Mahmoodi (MSE, 2009)

Improved write margin 6T-SRAM for low supply voltage applications. - Farshad Moradi; Dag T. Wisland; Hamid Mahmoodi; Tuan Vu Cao (SoCC, 2009)

Ultra Low-Power Clocking Scheme Using Energy Recovery and Clock Gating. - Hamid Mahmoodi; Vishy Tirumalashetty; Matthew Cooke; Kaushik Roy 001 (IEEE Trans. Very Large Scale Integr. Syst., 2009)

Data-dependant sense-amplifier flip-flop for low power applications. - Farshad Moradi; Charles Augustine; Ashish Goel; Georgios Karakonstantis; Tuan Vu Cao; Dag T. Wisland; Hamid Mahmoodi; Kaushik Roy 001 (CICC, 2010)

Reliability analysis of power gated SRAM under combined effects of NBTI and PBTI in nano-scale CMOS. - Anuj Pushkarna; Hamid Mahmoodi (ACM Great Lakes Symposium on VLSI, 2010)

New SRAM design using body bias technique for ultra low power applications. - Farshad Moradi; Dag T. Wisland; Hamid Mahmoodi; Yngvar Berg; Tuan Vu Cao (ISQED, 2010)

Comparison of performance parameters of SRAM designs in 16nm CMOS and CNTFET technologies. - Anuj Pushkarna; Sajna Raghavan; Hamid Mahmoodi (SoCC, 2010)

Thermal estimation for accurate estimation of impact of BTI aging effects on nano-scale SRAM circuits. - Ankitchandra Shah; Hamid Mahmoodi (SoCC, 2010)

Postsilicon Adaptation for Low-Power SRAM under Process Variation. - Minki Cho; Jason Schlessman; Hamid Mahmoodi; Marilyn Wolf; Saibal Mukhopadhyay (IEEE Des. Test Comput., 2010)

Low-overhead Fmax calibration at multiple operating points using delay-sensitivity-based path selection. - Somnath Paul; Hamid Mahmoodi; Swarup Bhunia (ACM Trans. Design Autom. Electr. Syst., 2010)

Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering. - Yongtao Wang; Hamid Mahmoodi; Lih-Yih Chiou; Hunsoo Choo; Jongsun Park 001; Woopyo Jeong; Kaushik Roy 001 (J. Signal Process. Syst., 2010)

Low-Power and Variation-Tolerant Memory Design. - Hamid Mahmoodi (Low-Power Variation-Tolerant Design in Nanometer Silicon, 2011)

Comparative analysis of copper and CNT interconnects for H-tree clock distribution. - Vish Ganti; Hamid Mahmoodi (ICCD, 2011)

Multi-level wordline driver for low power SRAMs in nano-scale CMOS technology. - Farshad Moradi; Georgios Panagopoulos; Georgios Karakonstantis; Dag T. Wisland; Hamid Mahmoodi; Jens Kargaard Madsen; Kaushik Roy 001 (ICCD, 2011)

Analysis of reliability of flip-flops under transistor aging effects in nano-scale CMOS technology. - Vikram G. Rao; Hamid Mahmoodi (ICCD, 2011)

Comparative BTI reliability analysis of SRAM cell designs in nano-scale CMOS technology. - Shreyas Kumar Krishnappa; Hamid Mahmoodi (ISQED, 2011)

An optimization method for NBTI-aware design of domino logic circuits in nano-scale CMOS. - Masaoud Houshmand Kaffashian; Reza Lotfi; Khalil Mafinezhad; Hamid Mahmoodi (IEICE Electron. Express, 2011)

Impact of NBTI on performance of domino logic circuits in nano-scale CMOS. - Masaoud Houshmand Kaffashian; Reza Lotfi; Khalil Mafinezhad; Hamid Mahmoodi (Microelectron. J., 2011)

Flip-flop design using novel pulse generation technique. - Farshad Moradi; Dag T. Wisland; Jens Kargaard Madsen; Hamid Mahmoodi (ICECS, 2012)

Impact of transistor aging effects on sense amplifier reliability in nano-scale CMOS. - Roberto Menchaca; Hamid Mahmoodi (ISQED, 2012)

Impact of technology scaling on performance of domino logic in nano-scale CMOS. - Abhishek Guar; Hamid Mahmoodi (VLSI-SoC, 2012)

Reliability enhancement of power gating transistor under time dependent dielectric breakdown. - Hamid Mahmoodi (VLSI-SoC, 2012)

Modeling read SNM considering both soft oxide breakdown and negative bias temperature instability. - Behrouz Afzal; Behzad Ebrahimi; Ali Afzali-Kusha; Hamid Mahmoodi (Microelectron. Reliab., 2012)

Impacts of NBTI/PBTI on performance of domino logic circuits with high-k metal-gate devices in nanoscale CMOS. - Masaoud Houshmand Kaffashian; Reza Lotfi; Khalil Mafinezhad; Hamid Mahmoodi (Microelectron. Reliab., 2012)

Domino logic designs for high-performance and leakage-tolerant applications. - Farshad Moradi; Tuan Vu Cao; Elena I. Vatajelu; Ali Peiravi; Hamid Mahmoodi; Dag T. Wisland (Integr., 2013)

An analytical model for read static noise margin including soft oxide breakdown, negative and positive bias temperature instabilities. - Behrouz Afzal; Behzad Ebrahimi; Ali Afzali-Kusha; Hamid Mahmoodi (Microelectron. Reliab., 2013)

Exploiting STT-NV technology for reconfigurable, high performance, low power, and low temperature functional unit design. - Adarsh Reddy Ashammagari; Hamid Mahmoodi; Houman Homayoun (DATE, 2014)

Reconfigurable STT-NV LUT-based functional units to improve performance in general-purpose processors. - Adarsh Reddy Ashammagari; Hamid Mahmoodi; Tinoosh Mohsenin; Houman Homayoun (ACM Great Lakes Symposium on VLSI, 2014)

Resistive Computation: A Critique. - Hamid Mahmoodi; Sridevi Srinivasan Lakshmipuram; Manish Arora; Yashar Asgarieh; Houman Homayoun; Bill Lin 001; Dean M. Tullsen (IEEE Comput. Archit. Lett., 2014)

Multi-level wordline driver for robust SRAM design in nano-scale CMOS technology. - Farshad Moradi; Georgios Panagopoulos; Georgios Karakonstantis; Hooman Farkhani; Dag T. Wisland; Jens Kargaard Madsen; Hamid Mahmoodi; Kaushik Roy 001 (Microelectron. J., 2014)

Robust FinFET SRAM design based on dynamic back-gate voltage adjustment. - Behzad Ebrahimi; Ali Afzali-Kusha; Hamid Mahmoodi (Microelectron. Reliab., 2014)

Hybrid STT-CMOS designs for reverse-engineering prevention. - Theodore Winograd; Hassan Salmani; Hamid Mahmoodi; Kris Gaj; Houman Homayoun (DAC, 2016)

Dynamic single and Dual Rail spin transfer torque look up tables with enhanced robustness under CMOS and MTJ process variations. - Aliyar Attaran; Hassan Salmani; Houman Homayoun; Hamid Mahmoodi (ICCD, 2016)

Comparative analysis of robustness of spin transfer torque based look up tables under process variations. - Ragh Kuttappa; Houman Homayoun; Hassan Salmani; Hamid Mahmoodi (ISCAS, 2016)

Preventing design reverse engineering with reconfigurable spin transfer torque LUT gates. - Theodore Winograd; Hassan Salmani; Hamid Mahmoodi; Houman Homayoun (ISQED, 2016)

Comparative analysis of hybrid Magnetic Tunnel Junction and CMOS logic circuits. - Darya Almasi; Houman Homayoun; Hassan Salmani; Hamid Mahmoodi (SoCC, 2016)

Power and energy reduction of racetrack-based caches by exploiting shared shift operations. - Seyed Saber Nabavi Larimi; Mehdi Kamal; Ali Afzali-Kusha; Hamid Mahmoodi (VLSI-SoC, 2016)

Reliability analysis of spin transfer torque based look up tables under process variations and NBTI aging. - Ragh Kuttappa; Houman Homayoun; Hassan Salmani; Hamid Mahmoodi (Microelectron. Reliab., 2016)

Read static noise margin aging model considering SBD and BTI effects for FinFET SRAMs. - Kolsoom Mehrabi; Behzad Ebrahimi; Roohollah Yarmand; Ali Afzali-Kusha; Hamid Mahmoodi (Microelectron. Reliab., 2016)

Static Design of Spin Transfer Torques Magnetic Look Up Tables for ASIC Designs. - Aliyar Attaran; Tyler David Sheaves; Praveen Kumar Mugula; Hamid Mahmoodi (ACM Great Lakes Symposium on VLSI, 2018)

Programmable Gates Using Hybrid CMOS-STT Design to Prevent IC Reverse Engineering. - Ted Winograd; Gaurav Shenoy; Hassan Salmani; Hamid Mahmoodi; Setareh Rafatirad; Houman Homayoun (ACM Trans. Design Autom. Electr. Syst., 2018)

On Custom LUT-based Obfuscation. - Gaurav Kolhe; Sai Manoj P. D.; Setareh Rafatirad; Hamid Mahmoodi; Avesta Sasan; Houman Homayoun (ACM Great Lakes Symposium on VLSI, 2019)

Deep RNN-Oriented Paradigm Shift through BOCANet: Broken Obfuscated Circuit Attack. - Fatemeh Tehranipoor; Nima Karimian; Mehran Mozaffari Kermani; Hamid Mahmoodi (ACM Great Lakes Symposium on VLSI, 2019)

Security and Complexity Analysis of LUT-based Obfuscation: From Blueprint to Reality. - Gaurav Kolhe; Hadi Mardani Kamali; Miklesh Naicker; Tyler David Sheaves; Hamid Mahmoodi; Sai Manoj P. D.; Houman Homayoun; Setareh Rafatirad; Avesta Sasan (ICCAD, 2019)

RotaSYN: Rotary Traveling Wave Oscillator SYNthesizer. - Ragh Kuttappa; Adarsha Balaji; Vasil Pano; Baris Taskin; Hamid Mahmoodi (IEEE Trans. Circuits Syst. I Regul. Pap., 2019)

Silicon validation of LUT-based logic-locked IP cores. - Gaurav Kolhe; Tyler Sheaves; Kevin Immanuel Gubbi; Tejas Kadale; Setareh Rafatirad; Sai Manoj P. D.; Avesta Sasan; Hamid Mahmoodi; Houman Homayoun (DAC, 2022)

Breaking the Design and Security Trade-off of Look-up-table-based Obfuscation. - Gaurav Kolhe; Tyler David Sheaves; Sai Manoj P. D.; Hamid Mahmoodi; Setareh Rafatirad; Avesta Sasan; Houman Homayoun (ACM Trans. Design Autom. Electr. Syst., 2022)