Dependability Analysis Using a Fault Injection Tool Based on Synthesizability of HDL Models. - Hamid R. Zarandi; Seyed Ghassem Miremadi; Ali Reza Ejlali (DFT, 2003)

A Hybrid Fault Injection Approach Based on Simulation and Emulation Co-operation. - Ali Reza Ejlali; Seyed Ghassem Miremadi; Hamid R. Zarandi; Ghazanfar Asadi; Siavash Bayat Sarmadi (DSN, 2003)

Fault injection into SRAM-based FPGAs for the analysis of SEU effects. - Ghazanfar Asadi; Seyed Ghassem Miremadi; Hamid R. Zarandi; Alireza Ejlali (FPT, 2003)

Fault Injection into Verilog Models for Dependability Evaluation of Digital Systems. - Hamid R. Zarandi; Seyed Ghassem Miremadi; Ali Reza Ejlali (ISPDC, 2003)

A Mixed-Mode Simulation-Based Environment to Test and Dependability Assessment of HDL Models. - Hamid R. Zarandi; Seyed Ghassem Miremadi; Shaahin Hessabi; Ali Reza Ejlali (ESA/VLSI, 2004)

Fault Detection Enhancement in Cache Memories Using a High Performance Placement Algorithm. - Hamid R. Zarandi; Seyed Ghassem Miremadi; Hamid Sarbazi-Azad (IOLTS, 2004)

Evaluation of Fault-Tolerant Designs Implemented on SRAM-Based FPGAs. - Ghazanfar Asadi; Seyed Ghassem Miremadi; Hamid R. Zarandi; Ali Reza Ejlali (PRDC, 2004)

A Highly Fault Detectable Cache Architecture for Dependable Computing. - Hamid R. Zarandi; Seyed Ghassem Miremadi (SAFECOMP, 2004)

Hierarchical Multiple Associative Mapping in Cache Memories. - Hamid R. Zarandi; Seyed Ghassem Miremadi (ECBS, 2005)

Soft Error Mitigation in Cache Memories of Embedded Systems by Means of a Protected Scheme. - Hamid R. Zarandi; Seyed Ghassem Miremadi (LADC, 2005)

Hierarchical Binary Set Partitioning in Cache Memories. - Hamid R. Zarandi; Hamid Sarbazi-Azad (J. Supercomput., 2005)

Hierarchical Set-Associate Cache for High-Performance and Low-Energy Architecture. - Hamid R. Zarandi; Seyed Ghassem Miremadi (J. Circuits Syst. Comput., 2006)

A fault-tolerant cache architecture based on binary set partitioning. - Hamid R. Zarandi; Seyed Ghassem Miremadi (Microelectron. Reliab., 2006)

Matrix Codes: Multiple Bit Upsets Tolerant Method for SRAM Memories. - Costas Argyrides; Hamid R. Zarandi; Dhiraj K. Pradhan (DFT, 2007)

Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs. - Hamid R. Zarandi; Seyed Ghassem Miremadi; Costas Argyrides; Dhiraj K. Pradhan (IPDPS, 2007)

Multiple Upsets Tolerance in SRAM Memory. - Costas Argyrides; Hamid R. Zarandi; Dhiraj K. Pradhan (ISCAS, 2007)

CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs. - Hamid R. Zarandi; Seyed Ghassem Miremadi; Costas Argyrides; Dhiraj K. Pradhan (ISCAS, 2007)

Soft Error Mitigation in Switch Modules of SRAM-based FPGAs. - Hamid R. Zarandi; Seyed Ghassem Miremadi; Dhiraj K. Pradhan; Jimson Mathew (ISCAS, 2007)

CAD-Directed SEU Susceptibility Reduction in FPGA Circuits Designs. - Hamid R. Zarandi; Seyed Ghassem Miremadi; Dhiraj K. Pradhan; Jimson Mathew (ISCAS, 2007)

SEU-Mitigation Placement and Routing Algorithms and Their Impact in SRAM-Based FPGAs. - Hamid R. Zarandi; Seyed Ghassem Miremadi; Dhiraj K. Pradhan; Jimson Mathew (ISQED, 2007)

Dependability evaluation of Altera FPGA-based embedded systems subjected to SEUs. - Hamid R. Zarandi; Seyed Ghassem Miremadi (Microelectron. Reliab., 2007)

A SEU-protected cache memory-based on variable associativity of sets. - Hamid R. Zarandi; Seyed Ghassem Miremadi (Reliab. Eng. Syst. Saf., 2007)

An Analysis of Fault Effects and Propagations in AVR Microcontroller ATmega103(L). - Alireza Rohani; Hamid R. Zarandi (ARES, 2009)

A Fault Injection Attitude based on Background Debug Mode in Embedded Systems. - Seyyed Amir Asghari; Hamid R. Zarandi; Hossein Pedram; Morteza Ansarinia; Mohammad Khademi (CDES, 2009)

Fault injection-based evaluation of a synchronous NoC router. - Ashkan Eghbal; Pooria M. Yaghini; Hossein Pedram; Hamid R. Zarandi (IOLTS, 2009)

Diagnosis of faults in template-based asynchronous circuits. - Behnam Ghavami; Hamid R. Zarandi; Arezoo Salarpour; Hossein Pedram (SoC, 2009)

Fault tolerance assessment of PIC microcontroller based on fault injection. - Ashkan Eghbal; Hamid R. Zarandi; Pooria M. Yaghini (LATW, 2009)

Process Variation Aware Performance Analysis of Asynchronous Circuits Considering Spatial Correlation. - Mohsen Raji; Behnam Ghavami; Hamid R. Zarandi; Hossein Pedram (PATMOS, 2009)

A New CLB Architecture for Tolerating SEU in SRAM-Based FPGAs. - Alireza Rohani; Hamid R. Zarandi (ReConFig, 2009)

An Adaptive Redundancy Oriented Method to Tolerate Soft Errors in SRAM-Based FPGAs Using Unused Resources. - Somayeh Bahramnejad; Hamid R. Zarandi (ARES, 2010)

Analysis of Transient Faults on a MIPS-Based Dual-Core Processor. - Iman Faraji; Moslem Didehban; Hamid R. Zarandi (ARES, 2010)

A decoder-based switch box to mitigate soft errors in SRAM-based FPGAs. - Hassan Ebrahimi; Morteza Saheb Zamani; Hamid R. Zarandi (ASP-DAC, 2010)

A Probabilistic Method to Detect Anomalies in Embedded Systems. - Mahroo Zandrahimi; Alireza Zarei; Hamid R. Zarandi (DFT, 2010)

Statistical Leakage Power Optimization of Asynchronous Circuits Considering Process Variations. - Mohsen Raji; Alireza Tajary; Behnam Ghavami; Hossein Pedram; Hamid R. Zarandi (PATMOS, 2010)

Investigation of Transient Fault Effects in an Asynchronous NoC Router. - Pooria M. Yaghini; Ashkan Eghbal; Hossein Pedram; Hamid R. Zarandi (PDP, 2010)

Two Efficient Software Techniques to Detect and Correct Control-Flow Errors. - Hamid R. Zarandi; Mohammad Maghsoudloo; Navid Khoshavi (PRDC, 2010)

Process variation-aware performance analysis of asynchronous circuits. - Mohsen Raji; Behnam Ghavami; Hossein Pedram; Hamid R. Zarandi (Microelectron. J., 2010)

Two effective methods to mitigate soft error effects in SRAM-based FPGAs. - Alireza Rohani; Hamid R. Zarandi (Microelectron. Reliab., 2010)

Performance modeling of n-dimensional mesh networks. - Pedram Rajabzadeh; Hamid Sarbazi-Azad; Hamid R. Zarandi; Ebrahim Khodaie; Hashem Hashemi Najaf-abadi; Mohamed Ould-Khaoua (Perform. Evaluation, 2010)

Soft Error Detection Technique in Multi-threaded Architectures Using Control-Flow Monitoring. - Mohammad Maghsoudloo; Hamid R. Zarandi; Saadat Pour-Mozafari; Navid Khoshavi (DSD, 2011)

An efficient, dynamically adaptive method to tolerate transient faults in multi-core systems. - Hananeh Aliee; Hamid R. Zarandi (EWDC, 2011)

CPU-aware, process-level redundancy to tolerate faults in multi-core. - Hananeh Aliee; Hamid R. Zarandi; Alireza Tajary (HPCS, 2011)

Control-flow error recovery using commodity multi-core architecture features. - Navid Khoshavi; Hamid R. Zarandi; Mohammad Maghsoudloo (IOLTS, 2011)

Fault-tolerance assessment and enhancement in SoCWire interface: A system-on-chip wire. - Ronak Salamat; Hamid R. Zarandi (IOLTS, 2011)

Low-Cost Software-Implemented Error Detection Technique. - Mohammad Maghsoudloo; Hamid R. Zarandi; Navid Khoshavi (ISED, 2011)

A Fault-Tolerant, Dynamically Scheduled Pipeline Structure for Chip Multiprocessors. - Hananeh Aliee; Hamid R. Zarandi (SAFECOMP, 2011)

Control-flow error detection using combining basic and program-level checking in commodity multi-core architectures. - Navid Khoshavi; Hamid R. Zarandi; Mohammad Maghsoudloo (SIES, 2011)

Mitigation of soft errors in SRAM-based FPGAs using CAD tools. - Somayeh Bahramnejad; Hamid R. Zarandi (Comput. Electr. Eng., 2011)

HVD: horizontal-vertical-diagonal error detecting and correcting code to protect against with soft errors. - Mostafa Kishani; Hamid R. Zarandi; Hossein Pedram; Alireza Tajary; Mohsen Raji; Behnam Ghavami (Des. Autom. Embed. Syst., 2011)

Investigation of transient fault effects in synchronous and asynchronous Network on Chip router. - Pooria M. Yaghini; Ashkan Eghbal; Hossein Pedram; Hamid R. Zarandi (J. Syst. Archit., 2011)

Mitigating soft errors in SRAM-based FPGAs by decoding configuration bits in switch boxes. - Hassan Ebrahimi; Morteza Saheb Zamani; Hamid R. Zarandi (Microelectron. J., 2011)

An adaptive method to tolerate soft errors in SRAM-based FPGAs. - Somayeh Bahramnejad; Hamid R. Zarandi (Sci. Iran., 2011)

Susceptibility Analysis of LEON3 Embedded Processor against Multiple Event Transients and Upsets. - Hamed Abbasitabar; Hamid R. Zarandi; Ronak Salamat (CSE, 2012)

A Fault-Tolerant Low-Energy Multi-Application Mapping onto NoC-based Multiprocessors. - Fatemeh Khalili; Hamid R. Zarandi (CSE, 2012)

Dirty data vulnerability mitigation by means of sharing management in cache coherence protocols. - Mohammad Maghsoudloo; Hamid R. Zarandi (DFT, 2012)

A fault-aware low-energy spare core allocation in networks-on-chip. - Fatemeh Khalili; Hamid R. Zarandi (NORCHIP, 2012)

Two effective methods to detect anomalies in embedded systems. - Mahroo Zandrahimi; Hamid R. Zarandi; Mohammad Hadi Mottaghi (Microelectron. J., 2012)

An efficient adaptive software-implemented technique to detect control-flow errors in multi-core architectures. - Mohammad Maghsoudloo; Hamid R. Zarandi; Navid Khoshavi (Microelectron. Reliab., 2012)

A Reliability-Aware Multi-application Mapping Technique in Networks-on-Chip. - Fatemeh Khalili; Hamid R. Zarandi (PDP, 2013)

A fault-tolerant core mapping technique in networks-on-chip. - Fatemeh Khalili; Hamid R. Zarandi (IET Comput. Digit. Tech., 2013)

A parallel clustering algorithm on the star graph and its performance. - Hamid Sarbazi-Azad; Hamid R. Zarandi; Mahdi Fazeli (Math. Comput. Model., 2013)

A Fast and Accurate Fault Tree Analysis Based on Stochastic Logic Implemented on Field-Programmable Gate Arrays. - Hananeh Aliee; Hamid R. Zarandi (IEEE Trans. Reliab., 2013)

Fxy: a Hierarchical Routing Algorithm to Balance Performance and Fault Tolerance in Networks-on-Chip. - Saleh Fakhrali; Hamid R. Zarandi (J. Circuits Syst. Comput., 2014)

Reliability improvement in private non-uniform cache architecture using two enhanced structures for coherence protocols and replacement policies. - Mohammad Maghsoudloo; Hamid R. Zarandi (Microprocess. Microsystems, 2014)

DFTS: A dynamic fault-tolerant scheduling for real-time tasks in multicore processors. - Mohammad Hadi Mottaghi; Hamid R. Zarandi (Microprocess. Microsystems, 2014)

Cache vulnerability mitigation using an adaptive cache coherence protocol. - Mohammad Maghsoudloo; Hamid R. Zarandi (J. Supercomput., 2014)

Probabilistic analysis of dynamic and temporal fault trees using accurate stochastic logic gates. - Elham Cheshmikhani; Hamid R. Zarandi (Microelectron. Reliab., 2015)

Design space exploration of non-uniform cache access for soft-error vulnerability mitigation. - Mohammad Maghsoudloo; Hamid R. Zarandi (Microelectron. Reliab., 2015)

Accelerating Dynamic Fault Tree Analysis Based on Stochastic Logic Utilizing GPGPUs. - Elham Cheshmikhani; Hamid R. Zarandi (PDP, 2016)

Gate Merging: An NBTI Mitigation Method to Eliminate Critical Internal Nodes in Digital Circuits. - Maryam Ghane; Hamid R. Zarandi (PDP, 2016)

A Cluster-Based Method to Detect and Correct Anomalies in Sensor Data of Embedded Systems. - Roghayeh Mojarad; Hossain Kordestani; Hamid R. Zarandi (PDP, 2016)

MWPF: A Deadlock Avoidance Fully Adaptive Routing Algorithm in Networks-on-Chip. - Kamran Nasiri; Hamid R. Zarandi (PDP, 2016)

An Efficient Soft Error Detection in Multicore Processors Running Server Applications. - Alireza Tajary; Hamid R. Zarandi (PDP, 2016)

Postponing wearout failures in chip multiprocessors using thermal management and thread migration. - Elham Kashefi; Hamid R. Zarandi; Ann Gordon-Ross (ReCoSoC, 2016)

Leveraging the Potential of Control-Flow Error Resilient Techniques in Multithreaded Programs. - Navid Khoshavi; Mohammad Maghsoudloo; Hamid R. Zarandi (CoRR, 2016)

Double Stairs: A Fault-Tolerant Routing Algorithm for Networks-on-Chip. - Saleh Fakhrali; Hamid R. Zarandi (J. Circuits Syst. Comput., 2016)

Using instruction result locality and re-execution to mitigate silent data corruptions. - Alireza Tajary; Hamid R. Zarandi (Microelectron. Reliab., 2016)

Context-Aware Anomaly Detection in Embedded Systems. - Fatemeh Ehsani-Besheli; Hamid R. Zarandi (DepCoS-RELCOMEX, 2017)

Soft error analysis of MTJ-based logic-in-memory full adder: Threats and solution. - Javad Talafy; Hamid R. Zarandi (IOLTS, 2017)

Designing a differential 3R-2bit RRAM cell for enhancing read margin in cross-point RRAM arrays. - Mohammadreza Nakhkash; Hossein Bardareh; Farzaneh Zokaee; Hamid R. Zarandi (NORCAS, 2017)

Fast Fault Tree Analysis for Hybrid Uncertainties Using Stochastic Logic Implemented on Field-Programmable Gate Arrays: An Application in Quantitative Assessment and mitigation of Welding Defects Risk. - Shahab Shoar; Hamid R. Zarandi; Farnad Nasirzadeh; Elham Cheshmikhani (Qual. Reliab. Eng. Int., 2017)

DUSTER: DUal Source Write TERmination Method for STT-RAM Memories. - Saaed S. Faraji; Javad Talafy; Amir M. Hajisadeghi; Hamid R. Zarandi (DSD, 2018)

MOMENT: A Cross-Layer Method to Mitigate Multiple Event Transients in Combinational Circuits. - Amir M. Hajisadeghi; Hossein Bardareh; Hamid R. Zarandi (DSD, 2018)

A Low-Cost Soft Error Tolerant Read Circuit for Single/Multi-Level Cross-Point RRAM Arrays. - Hossein Bardareh; Amir M. Hajisadeghi; Hamid R. Zarandi (IOLTS, 2018)

AligneR: A Process-in-Memory Architecture for Short Read Alignment in ReRAMs. - Farzaneh Zokaee; Hamid R. Zarandi; Lei Jiang 001 (IEEE Comput. Archit. Lett., 2018)

A cross-layer aging-aware task scheduling approach for multiprocessor embedded systems. - Masoomeh Karami; Athena Abdi; Hamid R. Zarandi (Microelectron. Reliab., 2018)

HYSTERY: a hybrid scheduling and mapping approach to optimize temperature, energy consumption and lifetime reliability of heterogeneous multiprocessor systems. - Athena Abdi; Hamid R. Zarandi (J. Supercomput., 2018)

A Fast and Efficient Fault Tree Analysis Using Approximate Computing. - Salar Hashemi; Amir M. Hajisadeghi; Hamid R. Zarandi; Saadat Pour-Mozafari (EDCC, 2019)

Lifetime Reliability Enhancement in Multiprocessor Systems Through a Fine-Grained System-Level Approach. - Athena Abdi; Masoomeh Karami; Hamid R. Zarandi (J. Circuits Syst. Comput., 2019)

A meta heuristic-based task scheduling and mapping method to optimize main design challenges of heterogeneous multiprocessor embedded systems. - Athena Abdi; Hamid R. Zarandi (Microelectron. J., 2019)

ERPOT: A Quad-Criteria Scheduling Heuristic to Optimize Execution Time, Reliability, Power Consumption and Temperature in Multicores. - Athena Abdi; Alain Girault; Hamid R. Zarandi (IEEE Trans. Parallel Distributed Syst., 2019)

DYSCO: DYnamic Stepper Current InjectOr to improve write performance in STT-RAM memories. - Saeed Seyedfaraji; Amir M. Hajisadeghi; Javad Talafy; Hamid R. Zarandi (Microprocess. Microsystems, 2020)

IRHT: An SDC detection and recovery architecture based on value locality of instruction binary codes. - Alireza Tajary; Hamid R. Zarandi; Nader Bagherzadeh (Microprocess. Microsystems, 2020)

A High Performance, Multi-Bit Output Logic-in-Memory Adder. - Javad Talafy; Farzaneh Zokaee; Hamid R. Zarandi; Nader Bagherzadeh (IEEE Trans. Emerg. Top. Comput., 2021)

CLEAR: A Cross-Layer Soft Error Rate Reduction Method Based on Mitigating DETs in Nanoscale Combinational Logics. - Amir M. Hajisadeghi; Hamid R. Zarandi (Microprocess. Microsystems, 2021)

EARL: An Efficient Approximate HaRdware Framework for AcceLerating Fault Tree Analysis. - Salar Hashemi; Amir M. Hajisadeghi; Hamid R. Zarandi (DSD, 2022)

ThingsDND: IoT Device Failure Detection and Diagnosis for Multi-User Smart Homes. - Alireza Borhani; Hamid R. Zarandi (EDCC, 2022)

Stoch-IMC: A Bit-Parallel Stochastic In-Memory Computing Architecture Based on STT-MRAM. - Amir M. Hajisadeghi; Hamid R. Zarandi; Mahmoud Momtazpour (CoRR, 2024)

Online Soft Error Tolerance in ReRAM Crossbars for Deep Learning Accelerators. - Benyamin Khezeli; Hamid R. Zarandi; Elham Cheshmikhani (CoRR, 2024)

Approx-IMC: A general-purpose approximate digital in-memory computing framework based on STT-MRAM. - Amir M. Hajisadeghi; Mahmoud Momtazpour; Hamid R. Zarandi (Future Gener. Comput. Syst., 2024)

Optimizing Proof-of-Work Blockchain Network Communications Using Genetic Algorithm. - Arman Gheysari; Murtadha Almahdawi; Hamid R. Zarandi (CSICC, 2025)

A reliability framework for NB-IoT devices: Addressing transient faults and silent data corruptions. - Fatemeh Khojasteh Dana; Seyedeh Fatemeh Anvari; Hamid R. Zarandi (Comput. Electr. Eng., 2025)

An Empirical Fault Vulnerability Exploration of ReRAM-Based Process-in-Memory CNN Accelerators. - Aniseh Dorostkar; Hamed Farbeh; Hamid R. Zarandi (IEEE Trans. Reliab., 2025)

OptGM: An Optimized Gate Merging Method to Mitigate NBTI in Digital Circuits. - Maryam Ghane; Amir M. Hajisadeghi; Hamid R. Zarandi (CoRR, 2025)

Simultaneous optimization of network-on-chip to improve reliability and reduce average packet latency considering buffer size constraints. - Hesam Abdolhosseini; Hamid R. Zarandi; Arman Gheysari (J. Supercomput., 2025)