SLIP: a software environment for system level interactive partitioning. - Mark Beardslee; Chuck Kring; Rajeev Murgai; Hamid Savoj; Robert K. Brayton; A. Richard Newton (ICCAD, 1989)

Fast two-level logic minimizers for multi-level logic synthesis. - Hamid Savoj; Abdul A. Malik; Robert K. Brayton (ICCAD, 1989)

The Use of Observability and External Don't Cares for the Simplification of Multi-Level Networks. - Hamid Savoj; Robert K. Brayton (DAC, 1990)

Implicit State Enumeration of Finite State Machines Using BDDs. - Hervé J. Touati; Hamid Savoj; Bill Lin 001; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCAD, 1990)

Observability Relations and Observability Don't Cares. - Hamid Savoj; Robert K. Brayton (ICCAD, 1991)

Extracting Local Don't Cares for Network Optimization. - Hamid Savoj; Robert K. Brayton; Hervé J. Touati (ICCAD, 1991)

Delay Optimization of Combinational Logic Circuits By Clustering and Partial Collapsing. - Hervé J. Touati; Hamid Savoj; Robert K. Brayton (ICCAD, 1991)

Boolean matching in logic synthesis. - Hamid Savoj; Mário J. Silva; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (EURO-DAC, 1992)

Sequential Circuit Design Using Synthesis and Optimization. - Ellen Sentovich; Kanwar Jit Singh; Cho W. Moon; Hamid Savoj; Robert K. Brayton; Alberto L. Sangiovanni-Vincentelli (ICCD, 1992)

Chemical Function Queries for 3D Database Search. - Jonathan Greene; Scott D. Kahn; Hamid Savoj; Peter Sprague; Steven L. Teig (J. Chem. Inf. Comput. Sci., 1994)

LEOPARD: a Logical Effort-based fanout OPtimizer for ARea and Delay. - Peyman Rezvani; Amir H. Ajami; Massoud Pedram; Hamid Savoj (ICCAD, 1999)

Physical synthesis for ASIC datapath circuits. - Terry Tao Ye; Samit Chaudhuri; F. Huang; Hamid Savoj; Giovanni De Micheli (ISCAS (3), 2002)

An Efficient Linear Time Algorithm for Scan Chain Optimization and Repartitioning. - David Berthelot; Samit Chaudhuri; Hamid Savoj (ITC, 2002)

Combinational techniques for sequential equivalence checking. - Hamid Savoj; David Berthelot; Alan Mishchenko; Robert K. Brayton (FMCAD, 2010)

Sequential Equivalence Checking for Clock-Gated Circuits. - Hamid Savoj; Alan Mishchenko; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014)

m-Inductive Property of Sequential Circuits. - Hamid Savoj; Alan Mishchenko; Robert K. Brayton (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016)