A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection. - Sung-Yong Cho; Sungwoo Kim 001; Min-Seong Choo; Jinhyung Lee; Han-Gon Ko; Sungchun Jang; Sang-Hyeok Chu; Woo-Rham Bae; Yoonsoo Kim; Deog-Kyoon Jeong (ESSCIRC, 2015)

A theoretical analysis of phase shift in pulse injection-locked oscillators. - Jinhyung Lee; Sungwoo Kim 001; Min-Seong Choo; Sung-Yong Cho; Han-Gon Ko; Deog-Kyoon Jeong (ISCAS, 2016)

29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibration. - Sungwoo Kim 001; Han-Gon Ko; Sung-Yong Cho; Jinhyung Lee; Soyeong Shin; Min-Seong Choo; Hankyu Chi; Deog-Kyoon Jeong (ISSCC, 2017)

A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate All-Digital Injection-Locked Clock and Data Recovery with Maximum Timing-Margin Tracking Loop. - Min-Seong Choo; Han-Gon Ko; Sung-Yong Cho; Kwangho Lee; Deog-Kyoon Jeong (A-SSCC, 2018)

A 2.5-5.6 GHz Subharmonically Injection-Locked All-Digital PLL With Dual-Edge Complementary Switched Injection. - Sung-Yong Cho; Sungwoo Kim 001; Min-Seong Choo; Han-Gon Ko; Jinhyung Lee; Woo-Rham Bae; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. I Regul. Pap., 2018)

An Optimum Injection-Timing Tracking Loop for 5-GHz, 1.13-mW/GHz RO-Based Injection-Locked PLL With 152-fs Integrated Jitter. - Min-Seong Choo; Han-Gon Ko; Sung-Yong Cho; Kwangho Lee; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

25-Gb/s Clocked Pluggable Optics for High-Density Data Center Interconnections. - Gyu-Seob Jeong; Jeongho Hwang; Hong-Seok Choi; Hyungrok Do; Daehyun Koh; Daeyoung Yun; Jinhyung Lee; Kwanseo Park; Han-Gon Ko; Kwangho Lee; Jiho Joo; Gyungock Kim; et al. (IEEE Trans. Circuits Syst. II Express Briefs, 2018)

A Design of Data Path Based on CMOS Logic for a 72-Gb/s PAM-4 Transmitter in 28-nm CMOS. - Moon-Chul Choi; Haram Ju; Han-Gon Ko; Deog-Kyoon Jeong (ICEIC, 2019)

A 370-fJ/b, 0.0056 mm2/DQ, 4.8-Gb/s DQ Receiver for HBM3 with a Baud-Rate Self-Tracking Loop. - Han-Gon Ko; Soyeong Shin; Chan-Ho Kye; Sang-Yoon Lee 006; Jaekwang Yun; Hae-Kang Jung; Doobock Lee; Suhwan Kim 001; Deog-Kyoon Jeong (VLSI Circuits, 2019)

Reference Spur Reduction Techniques for a Phase-Locked Loop. - Han-Gon Ko; Woo-Rham Bae; Gyu-Seob Jeong; Deog-Kyoon Jeong (IEEE Access, 2019)

A 10-Gb/s, 0.03-mm2, 1.28-pJ/bit Half-Rate Injection-Locked CDR With Path Mismatch Tracking Loop in a 28-nm CMOS Technology. - Min-Seong Choo; Kwanseo Park; Han-Gon Ko; Sung-Yong Cho; Kwangho Lee; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2019)

A 2.5-28 Gb/s Multi-Standard Transmitter With Two-Step Time-Multiplexing Driver. - Moon-Chul Choi; Deog-Kyoon Jeong; Sung-Yong Cho; Minkyo Shim; Byungmin Kim; Han-Gon Ko; Haram Ju; Kwanseo Park; Hyojun Kim; Kwandong Kim (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

A 15-GHz, 17.8-mW, 213-fs Injection-Locked PLL With Maximized Injection Strength Using Adjustment of Phase Domain Response. - Min-Seong Choo; Yeonggeun Song; Sung-Yong Cho; Han-Gon Ko; Kwanseo Park; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2019)

6.7 An 8Gb/s/µm FFE-Combined Crosstalk-Cancellation Scheme for HBM on Silicon Interposer with 3D-Staggered Channels. - Han-Gon Ko; Soyeong Shin; Jonghyun Oh; Kwanseo Park; Deog-Kyoon Jeong (ISSCC, 2020)

6.5 A 6.4-to-32Gb/s 0.96pJ/b Referenceless CDR Employing ML-Inspired Stochastic Phase-Frequency Detection Technique in 40nm CMOS. - Kwanseo Park; Minkyo Shim; Han-Gon Ko; Deog-Kyoon Jeong (ISSCC, 2020)

22.6 A 0.8-to-2.3GHz Quadrature Error Corrector with Correctable Error Range of 101.6ps Using Minimum Total Delay Tracking and Asynchronous Calibration On-Off Scheme for DRAM Interface. - Soyeong Shin; Han-Gon Ko; Sungchun Jang; Dongkyun Kim; Deog-Kyoon Jeong (ISSCC, 2020)

A 0.1-pJ/b/dB 28-Gb/s Maximum-Eye Tracking, Weight-Adjusting MM CDR and Adaptive DFE with Single Shared Error Sampler. - Moon-Chul Choi; Han-Gon Ko; Jonghyun Oh; Hye-Yoon Joo; Kwangho Lee; Deog-Kyoon Jeong (VLSI Circuits, 2020)

A 0.83-pJ/Bit 6.4-Gb/s HBM Base Die Receiver Using a 45° Strobe Phase for Energy-Efficient Skew Compensation. - Sangyoon Lee 006; Han-Gon Ko; Joo-Hyung Chae; Soyeong Shin; Jaekwang Yun; Deog-Kyoon Jeong; Suhwan Kim 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A 0.45 pJ/b, 6.4 Gb/s Forwarded-Clock Receiver With DLL-Based Self-Tracking Loop for Unmatched Memory Interfaces. - Soyeong Shin; Han-Gon Ko; Chan-Ho Kye; Sang-Yoon Lee 006; Jaekwang Yun; Doobock Lee; Hae-Kang Jung; Suhwan Kim 001; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2020)

A Maximum-Eye-Tracking CDR With Biased Data-Level and Eye Slope Detector for Near-Optimal Timing Adaptation. - Hye-Yoon Joo; Jinhyung Lee; Haram Ju; Han-Gon Ko; Jungmin Yoon; Byungjun Kang; Deog-Kyoon Jeong (IEEE Trans. Very Large Scale Integr. Syst., 2020)

A 22-Gb/s 0.95-pJ/b Energy-Efficient Voltage-Mode Transmitter With Time-Based Feedforward Equalization in a 28-nm CMOS. - Chan-Ho Kye; Han-Gon Ko; Jinhyung Lee; Deog-Kyoon Jeong (IEEE Trans. Very Large Scale Integr. Syst., 2020)

0.37-pJ/b/dB PAM-4 Transmitter and Adaptive Receiver with Fixed Data and Threshold Levels for 12-m Automotive Camera Link. - Woonghee Lee 005; Minkyo Shim; Yunhee Lee; Heejin Yang; Han-Gon Ko; Woo-Seok Choi; Deog-Kyoon Jeong (ESSCIRC, 2021)

A 10 Gb/s PAM-4 Transmitter With Feed-Forward Implementation of Tomlinson-Harashima Precoding in 28 nm CMOS. - Byungjun Kang; Gyu-Seob Jeong; Jeongho Hwang; Kwanseo Park; Hyungrok Do; Hyojun Kim; Han-Gon Ko; Moon-Chul Choi; Deog-Kyoon Jeong (IEEE Access, 2021)

A PVT Variation-Robust All-Digital Injection-Locked Clock Multiplier With Real-Time Offset Tracking Using Time-Division Dual Calibration. - Min-Seong Choo; Sungwoo Kim 001; Han-Gon Ko; Sung-Yong Cho; Kwanseo Park; Jinhyung Lee; Soyeong Shin; Hankyu Chi; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2021)

0.76-mW/pF/GHz, 7-GHz Quadrature Resonant Clock With Frequency Tuning Capacitor and Amplitude Control Feedback Loop. - Chang-Soo Yoon; Han-Gon Ko; Byung-Jun Kang; Jung-Woo Sull; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

A -247.1 dB FoM, -77.9dBc Reference Spur Ring-Oscillator-Based Injection-Locked Clock Multiplier with Multi-Phase-Based Calibration. - Yeonggeun Song; Kyoungjoon Ha; Han-Gon Ko; Min-Seong Choo; Deog-Kyoon Jeong (ESSCIRC, 2022)

A 68.7-fJ/b/mm 375-GB/s/mm Single-Ended PAM-4 Interface with Per-Pin Training Sequence for the Next-Generation HBM Controller. - Jung-Hun Park; Kwang-Hoon Lee; Yongjae Lee; Jung-Woo Sull; Yoonho Song; Sanghee Lee 002; Hyeonseok Lee; Hoyeon Cho; Jonghyun Oh; Han-Gon Ko; Deog-Kyoon Jeong (VLSI Technology and Circuits, 2022)

Design Techniques for a 6.4-32-Gb/s 0.96-pJ/b Continuous-Rate CDR With Stochastic Frequency-Phase Detector. - Kwanseo Park; Minkyo Shim; Han-Gon Ko; Borivoje Nikolic; Deog-Kyoon Jeong (IEEE J. Solid State Circuits, 2022)

A 1.05-to-3.2 GHz All-Digital PLL for DDR5 Registering Clock Driver With a Self-Biased Supply-Noise-Compensating Ring DCO. - Yeonggeun Song; Han-Gon Ko; Changhyun Kim; Deog-Kyoon Jeong (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

A 32Gb/s/pin 0.51 pJ/b Single-Ended Resistor-less Impedance-Matched Transmitter with a T-Coil-Based Edge-Boosting Equalizer in 40nm CMOS. - Jung-Hun Park; Hyeonseok Lee; Hoyeon Cho; Sanghee Lee 002; Kwang-Hoon Lee; Han-Gon Ko; Deog-Kyoon Jeong (ISSCC, 2023)

A 3×12 -Gb/s 1.26-pJ/b Single-Ended PAM-3 Transmitter With Crosstalk Cancellation Technique in 28-nm CMOS. - Dongwoo Kang; Han-Gon Ko; Kwanseo Park (IEEE Trans. Circuits Syst. II Express Briefs, 2024)