Broadcast with mask on a massively parallel processing on a chip. - Hana Krichene; Mouna Baklouti; Mohamed Abid; Philippe Marquet; Jean-Luc Dekeyser (HPCS, 2012)

Master-Slave Control Structure for Massively Parallel System on Chip. - Hana Krichene; Mouna Baklouti; Mohamed Abid; Philippe Marquet; Jean-Luc Dekeyser (DSD, 2013)

SCAC-Net: Reconfigurable Interconnection Network in SCAC Massively Parallel SoC. - Hana Krichene; Mouna Baklouti; Philippe Marquet; Jean-Luc Dekeyser; Mohamed Abid (PDP, 2016)

SCAC: Weakly-coupled execution model for massively parallel systems. - Hana Krichene; Mouna Baklouti; Philippe Marquet; Jean-Luc Dekeyser; Mohamed Abid (Microprocess. Microsystems, 2019)

DSM: Data Sharing Management system for in-vehicle communication. - Hana Krichene; Paul Dubrulle; Raphael Millet (ISCC, 2021)

Analysis of on-chip communication properties in accelerator architectures for deep neural networks. - Hana Krichene; Jean-Marc Philippe (NOCS, 2021)

AINoC: New Interconnect for Future Deep Neural Network Accelerators. - Hana Krichene; Rohit Prasad; Ayoub Mouhagir (DASIP, 2023)

A dataflow architecture with distributed control for DNN acceleration. - Hana Krichene; Rohit Prasad (MECO, 2024)

HT-NoC: Reconfigurable High Throughput Network-on-Chip for AI Dataflow Accelerators. - Mohamed Amine Zhiri; Hana Krichene; Chiara Sandionigi; Sébastien Pillement (ARC, 2025)

Efficient FPGA Implementation of ViT Non-linear Functions. - Le Nam Hieu Nguyen; Hana Krichene (DASIP, 2025)