Analysis of SNR Metrics for a Typical Underwater Acoustic OFDM System. - Gang Qiao; Yuzhu Xiao; Lei Wan; Xiaolong Guo; Hanbo Jia (IEEE Access, 2019)

Low-Complexity Doppler Compensation Algorithm for Underwater Acoustic OFDM Systems With Nonuniform Doppler Shifts. - Lu Ma; Hanbo Jia; Songzuo Liu; Imran Ullah Khan (IEEE Commun. Lett., 2020)

Fine Doppler scale estimations for an underwater acoustic CP-OFDM system. - Lei Wan; Hanbo Jia; Feng Zhou 012; Muhammad Muzzammil; Tao Li; Yi Huang (Signal Process., 2020)

A 64Gbps 1.36 Vppd 1.44pJ/b Fully CMOS-Style Transmitter with Active Hybrid Driver in 28nm CMOS. - Da Fu; Danyu Wu; Xuan Guo; Hanbo Jia; Jie Fu; Shan Lu; Xinyu Liu 004 (MWSCAS, 2023)

STAR-RIS Enabled Downlink Secure NOMA Network Under Imperfect CSI of Eavesdroppers. - Hanbo Jia; Lin Ma 001; Shahrokh Valaee (IEEE Commun. Lett., 2023)

Joint Secure and Covert Beamforming Design in Dual-Functional Radar-Communication Systems. - Hanbo Jia; Lin Ma 001; Shuyi Chen; Danyang Qin (ICC Workshops, 2024)

Energy leakage in OFDM sparse channel estimation: The drawback of OMP and the application of image deblurring. - Gang Qiao; Xizhu Qiang; Lei Wan; Hanbo Jia (Digit. Commun. Networks, 2024)

A wideband front-end with integrated high-voltage assisted input buffer for high-speed ADC. - Zilin Jiang; Danyu Wu; Xuan Guo; Hanbo Jia; Shuangbao Jia; Heping Ma; Kai Sun; Xinyu Liu 004 (IEICE Electron. Express, 2024)

A 1.25-GS/s 14-bit pipelined ADC using a current-feedback flipped input buffer and large dither technique to achieve high linearity. - Zeyu Li; Xuan Guo; Hanbo Jia; Xinyu Liu 004 (IEICE Electron. Express, 2024)

An interstage gain calibration technique for pipelined ADCs exploiting complementary dithering and calibration windows detector. - Huaiyu Zhai; Hanbo Jia; Xuan Guo; Zilin Jiang; Yuzhen Zhang; Dandan Wang; Jin Wu (IEICE Electron. Express, 2024)

A 1.25-GS/s 10-bit single-channel ring amplifier-based pipelined ADC in 28-nm CMOS. - Heng Zhang 037; Xuan Guo; Ben He; Hanbo Jia; Xinyu Liu 004 (Microelectron. J., 2024)

A 12bit 1.6 GS/s pipelined ADC with multi-level dither injection achieving 68 dB SFDR over PVT. - Feitong Wu; Hanbo Jia; Xuan Guo; Zilin Jiang; Xinyu Liu 004 (Microelectron. J., 2024)

Physical Layer Security Optimization With Cramér-Rao Bound Metric in ISAC Systems Under Sensing-Specific Imperfect CSI Model. - Hanbo Jia; Xiaoshuai Li; Lin Ma 001 (IEEE Trans. Veh. Technol., 2024)

A 28-nm Dual-Mode Explicit Class-F₂₃ VCO With Low-Loss CM Return Path Achieving 70-400-kHz 1/f³ PN Corner Over 4.9-7.3-GHz TR. - Shan Lu; Danyu Wu; Xuan Guo; Hanbo Jia; Yong Chen 005; Xinyu Liu 004 (IEEE Trans. Very Large Scale Integr. Syst., 2024)

Large-Scale Decentralized UAV Full-Duplex Ad-Hoc Networking: Architecture, Clustering and Access. - Suning Liu; Liang Ye; Hanbo Jia; Guanqiao Qu; Xiaomeng Luo; Weixiao Meng 001 (IEEE Netw., 2024)

Robust Beamforming Design for Covert Integrated Sensing and Communication in the Presence of Multiple Wardens. - Hanbo Jia; Lin Ma 001; Danyang Qin (IEEE Trans. Veh. Technol., 2024)

A 16-Bit 5 GS/s DAC With Redundant-MSB-Based Digital Pre-Distortion Achieving SFDR >61 dBc Up to 2.4 GHz in 40-nm CMOS. - Xing Li; Lei Zhou 014; Xuan Guo; Hanbo Jia; Danyu Wu; Jin Wu; Xinyu Liu 004 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A 500MS/s 14-bit Pipelined ADC With Startup Protection Circuit in 40 nm CMOS. - Ben He; Xuan Guo; Hanbo Jia; Kai Sun; Xinyu Liu 004 (IEEE Access, 2025)

A dither-based background calibration circuit for pipelined ADCs in 40 nm CMOS. - Ben He; Xuan Guo; Hanbo Jia; Kai Sun; Lei Zhou 014; Zhijie Chen; Xinyu Liu 004 (IEICE Electron. Express, 2025)

An input buffer with opamp-based bootstrap circuit and cross-coupled substrate technique for 1.5-GS/s pipelined ADC in 40-nm CMOS process. - Zeyu Li; Fangyuan Xu; Xuan Guo; Hanbo Jia; Kai Sun; Xinyu Liu 004 (IEICE Electron. Express, 2025)

A high-speed single channel reconfigurable 1-GS/s to 1.5-GS/s, 8-bit to 6-bit SAR ADC in 28 nm CMOS. - Qing Su; Xuan Guo; Hanbo Jia; Yihan Li; Kai Sun; Xinyu Liu 004 (IEICE Electron. Express, 2025)

A 14-GS/s 8-bit time-interleaved SAR ADC with multi-path bootstrapped switch and low-jitter sampling PLL in 28-nm CMOS. - Jiawei Ding; Xuan Guo; Shan Lu; Qing Su; Tao liu; Hanbo Jia; Yihan Li; Xinyu Liu 004 (Microelectron. J., 2025)

A 100-MHz bandwidth continuous-time sigma-delta ADC with 1 V supply in 28 nm CMOS. - Ben He; Xuan Guo; Hanbo Jia; Xinyu Liu 004 (Microelectron. J., 2025)

A 500 MS/s 12b single channel SAR-assisted pipelined ADC with two-stage open-loop dynamic amplifier. - Qing Su; Xuan Guo; Hanbo Jia; Heping Ma; Linzhen Wu; Kai Sun; Xinyu Liu 004 (Microelectron. J., 2025)

A genetic algorithm-based capacitor mismatch calibration scheme for SAR ADCs. - Yuzhen Zhang; Xuan Guo; Hanbo Jia; Li Luo; Linzhen Wu; Dandan Wang; Xinyu Liu 004 (Microelectron. J., 2025)

Quantity Analysis Method for Text-Based Chip Test Datasets from Automated Test Equipment. - Jie Fu; Kai Sun; Hanbo Jia; Da Fu; Jingyuan Xu; Xuan Guo (J. Electron. Test., 2025)

A Quad-Core VCO Incorporating Area-Saving Folded S-Shaped Tail Filtering in 28-nm CMOS. - Shan Lu; Danyu Wu; Xuan Guo; Hanbo Jia; Yong Chen 005; Xinyu Liu 004 (IEEE Trans. Very Large Scale Integr. Syst., 2025)

Illegal Sensing Suppression for Integrated Sensing and Communication System. - Hanbo Jia; Rangang Zhu; Andrea Sciarrone; Lin Ma 001 (IEEE Internet Things J., 2025)

A 25-GS/s 8-bit Current-Steering DAC With ADC-Based Duty-Cycle Detection in 40-nm CMOS. - Xing Li; Lei Zhou 014; Xuan Guo; Hanbo Jia; Danyu Wu; Jin Wu; Xinyu Liu 004 (IEEE Trans. Very Large Scale Integr. Syst., 2025)