Rosetta: A Realistic High-Level Synthesis Benchmark Suite for Software Programmable FPGAs. - Yuan Zhou; Udit Gupta; Steve Dai; Ritchie Zhao; Nitish Kumar Srivastava; Hanchen Jin; Joseph Featherston; Yi-Hsiang Lai; Gai Liu; Gustavo Angarita Velasquez; Wenping Wang; Zhiru Zhang (FPGA, 2018)

Designing Secure Cryptographic Accelerators with Information Flow Enforcement: A Case Study on AES. - Zhenghong Jiang; Hanchen Jin; G. Edward Suh; Zhiru Zhang (DAC, 2019)

Tensaurus: A Versatile Accelerator for Mixed Sparse-Dense Tensor Computations. - Nitish Kumar Srivastava; Hanchen Jin; Shaden Smith; Hongbo Rong; David H. Albonesi; Zhiru Zhang (HPCA, 2020)

MatRaptor: A Sparse-Sparse Matrix Multiplication Accelerator Based on Row-Wise Product. - Nitish Kumar Srivastava; Hanchen Jin; Jie Liu 072; David H. Albonesi; Zhiru Zhang (MICRO, 2020)

Vesper: A Versatile Sparse Linear Algebra Accelerator With Configurable Compute Patterns. - Hanchen Jin; Zichao Yue; Zhongyuan Zhao 004; Yixiao Du; Chenhui Deng; Nitish Srivastava; Zhiru Zhang (IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2025)