The ROM Design with Half Grouping Compression Method for Chip Area and Power Consumption Reduction. - Ki-Sang Jung; Kang-Jik Kim; Yong-Eun Kim; Jin-Gyun Chung; Ki-Hyun Pyun; Jong-Yeol Lee; Hang-Geun Jeong; Seong Ik Cho (IEICE Trans. Electron., 2009)

Design of a CMOS Current-mode Squaring Circuit for Training Analog Neural Networks. - So-Hyeon Park; Jae-Hee Lee; Hang-Geun Jeong; Donggu Im (ISOCC, 2020)

A Current-link CMOS Analog Neuron with Simplified Synapse Using a Merged Switch Array. - Hee-Yeon Yang; Yu-Jin Noh; Sung-Ho Lee; Geun-Won Kim; Hang-Geun Jeong; Donggu Im (ISOCC, 2020)