Microwave penetration depth measurement for high Tc superconductors by dielectric resonators. - Hang-Ting Lue; Juh-Tzeng Lue; Tseung-Yuen Tseng (IEEE Trans. Instrum. Meas., 2002)

State-of-the-art flash memory devices and post-flash emerging memories. - Chihyuan Lu; Hang-Ting Lue; Yichou Chen (Sci. China Inf. Sci., 2011)

On Trading Wear-leveling with Heal-leveling. - Yu-Ming Chang; Yuan-Hao Chang 001; Jian-Jia Chen; Tei-Wei Kuo; Hsiang-Pang Li; Hang-Ting Lue (DAC, 2014)

Layer-Aware Program-and-Read Schemes for 3D Stackable Vertical-Gate BE-SONOS NAND Flash Against Cross-Layer Process Variations. - Chun-Hsiung Hung; Meng-Fan Chang; Yih-Shan Yang; Yao-Jen Kuo; Tzu-Neng Lai; Shin-Jang Shen; Jo-Yu Hsu; Shuo-Nan Hung; Hang-Ting Lue; Yen-Hao Shih; Shih-Lin Huang; Ti-Wen Chen; et al. (IEEE J. Solid State Circuits, 2015)

Study of the Walk-Out Effect of Junction Breakdown Instability of the High-Voltage Depletion-Mode N-Channel MOSFET for NAND Flash Peripheral Device and an Efficient Layout Solution. - Chieh Roger Lo; Teng-Hao Yeh; Wei-Chen Chen; Hang-Ting Lue; Keh-Chung Wang; Chih-Yuan Lu; Yao-Wen Chang; Yung-Hsiang Chen; Chu-Yung Liu (IRPS, 2020)

Introduction of Non-Volatile Computing In Memory (nvCIM) by 3D NAND Flash for Inference Accelerator of Deep Neural Network (DNN) and the Read Disturb Reliability Evaluation : (Invited Paper). - Hang-Ting Lue; Po-Kai Hsu; Keh-Chung Wang; Chih-Yuan Lu (IRPS, 2020)

Write-In-Place Operation and It's Advantages to Upgrade the 3D AND-type Flash Memory Performances. - Hang-Ting Lue; Tzu-Hsuan Hsu; Cheng-Lin Sung; Teng-Hao Yeh; Keh-Chung Wang; Chih-Yuan Lu (IMW, 2021)

First Study of P-Channel Vertical Split-Gate Flash Memory Device with Various Electron and Hole Injection Methods and Potential Future Possibility to Enable Functional Memory Circuits. - Cheng-Lin Sung; Hang-Ting Lue; Wei-Chen Chen; Tzu-Hsuan Hsu; Keh-Chung Wang; Chih-Yuan Lu (IMW, 2021)

Robust Brain-Inspired Computing: On the Reliability of Spiking Neural Network Using Emerging Non-Volatile Synapses. - Ming-Liang Wei; Hussam Amrouch; Cheng-Lin Sung; Hang-Ting Lue; Chia-Lin Yang; Keh-Chung Wang; Chih-Yuan Lu (IRPS, 2021)

Design of Computing-in-Memory (CIM) with Vertical Split-Gate Flash Memory for Deep Neural Network (DNN) Inference Accelerator. - Hang-Ting Lue; Han-Wen Hu; Tzu-Hsuan Hsu; Po-Kai Hsu; Keh-Chung Wang; Chih-Yuan Lu (ISCAS, 2021)

First Experimental Study of Floating-Body Cell Transient Reliability Characteristics of Both N- and P-Channel Vertical Gate-All-Around Devices with Split-Gate Structures. - Cheng-Lin Sung; Sheng-Ting Fan; Hang-Ting Lue; Wei-Chen Chen; Pei-Ying Du; Teng-Hao Yeh; Keh-Chung Wang; Chih-Yuan Lu (IRPS, 2022)

A Simulation Study of Scaling Capability toward 10nm for the 3D Stackable Gate-Controlled Thyristor (GCT) DRAM Device. - Wei-Chen Chen; Hang-Ting Lue; Tzu-Hsuan Hsu; Keh-Chung Wang; Chih-Yuan Lu (IMW, 2023)

Chip Demonstration of a High-Density (43Gb) and High-Search-Bandwidth (300Gb/s) 3D NAND Based In-Memory Search Accelerator for Ternary Content Addressable Memory (TCAM) and Proximity Search of Hamming Distance. - Chih-Chang Hsieh; Hang-Ting Lue; Yung-Chun Li; Shuo-Nan Hung; Chun-Hsiung Hung; Keh-Chung Wang; Chih-Yuan Lu (VLSI Technology and Circuits, 2023)

Improved 3D DRAM Design Based on Gate-Controlled Thyristor Featuring Two Asymmetrical Horizontal WL's and Vertical BL for Better Cell Size Scaling and Array Selection. - Wei-Chen Chen; Hang-Ting Lue; Ming-Hung Wu; Yu-Tang Lin; Keh-Chung Wang; Chih-Yuan Lu (IMW, 2024)

Multi-Gate Access Transistor to Minimize GIDL Leakage Current for Scaling 2-tier Stacked 4F2 DRAM Below Equivalent 10nm Node. - Hang-Ting Lue; Wei-Chen Chen; Yu-Tang Lin; Keh-Chung Wang; Chih-Yuan Lu (IMW, 2024)

Charge Loss Improvement in 3D Flash Memory by Molecular Oxidation of Tunneling Oxide. - Pei-Ci Jhang; Chi-Pin Lu; Jung-Yu Shieh; Ling-Wu Yang; Tahone Yang; Kuang-Chao Chen; Hang-Ting Lue; Pei-Ying Du; Chih-Yuan Lu (IRPS, 2024)

A Novel 3D Stacked Vertical-Channel High-Voltage Peripheral Transistor for Largely Scaled the WL Driver Circuit of 1000-layer 3D NAND Flash. - Teng-Hao Yeh; Hang-Ting Lue; Wei-Chen Chen; Keh-Chung Wang; Chih-Yuan Lu (IMW, 2025)