Balancing Adder for error tolerant applications. - Matthew Weber; Mateja Putic; Hang Zhang 031; John C. Lach; Jiawei Huang 007 (ISCAS, 2013)

Low Power GPGPU Computation with Imprecise Hardware. - Hang Zhang 031; Mateja Putic; John C. Lach (DAC, 2014)

A low-power accuracy-configurable floating point multiplier. - Hang Zhang 031; Wei Zhang 044; John C. Lach (ICCD, 2014)

Adaptive front-end throttling for superscalar processors. - Wei Zhang 044; Hang Zhang 031; John C. Lach (ISLPED, 2014)

Dynamic core scaling: Trading off performance and energy beyond DVFS. - Wei Zhang 044; Hang Zhang 031; John C. Lach (ICCD, 2015)

Reducing dynamic energy of set-associative L1 instruction cache by early tag lookup. - Wei Zhang 044; Hang Zhang 031; John C. Lach (ISLPED, 2015)

Extending Performance-Energy Trade-offs Via Dynamic Core Scaling. - Wei Zhang 044; Hang Zhang 031; John C. Lach (IEEE Trans. Computers, 2021)