A 28nm 20.9-137.2 TOPS/W Output-Stationary SRAM Compute-in-Memory Macro Featuring Dynamic Look-ahead Zero Weight Skipping and Runtime Partial Sum Quantization. - Xiaofeng Hu; HanGyeol Mun; Jian Meng; Yuan Liao; Amitesh Sridharan; Jae-sun Seo (CICC, 2025)

Hybrid Systolic Array Accelerator with Optimized Dataflow for Edge Large Language Model Inference. - Chun-Ting Chen; HanGyeol Mun; Jian Meng; Mohamed S. Abdelfattah; Jae-sun Seo (CoRR, 2025)