A New Low-Voltage Full Adder Circuit. - Hanho Lee; Gerald E. Sobelman (Great Lakes Symposium on VLSI, 1997)

Digit-Serial DSP Library for Optimized FPGA Configuration. - Hanho Lee; Gerald E. Sobelman (FCCM, 1998)

FPGA Logic Block Architecture for Digit-Serial DSP Applications (Abstract). - Hanho Lee; Sarvesh Shrivastava; Gerald E. Sobelman (FPGA, 1998)

A Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor. - Lijun Gao; Sarvesh Shrivastava; Hanho Lee; Gerald E. Sobelman (FCCM, 1999)

VLSI design of Reed-Solomon decoder architectures. - Hanho Lee; Meng-Lin Yu; Leilei Song (ISCAS, 2000)

An Area-Efficient Euclidean Algorithm Block for Reed-Solomon Decoder. - Hanho Lee (ISVLSI, 2003)

Performance evaluation and optimal design for FPGA-based digit-serial DSP functions. - Hanho Lee; Gerald E. Sobelman (Comput. Electr. Eng., 2003)

High-speed VLSI architecture for parallel Reed-Solomon decoder. - Hanho Lee (IEEE Trans. Very Large Scale Integr. Syst., 2003)

VLSI Design Of Digit-Serial FPGA Architecture. - Hanho Lee; Gerald E. Sobelman (J. Circuits Syst. Comput., 2004)

An ultra high-speed Reed-Solomon decoder. - Hanho Lee (ISCAS (2), 2005)

An Evolvable Hardware System Under Uneven Environment. - In Ja Jeon; Phill-Kyu Rhee; Hanho Lee (KES (2), 2005)

Reconfigurable Power-Aware Scalable Booth Multiplier. - Hanho Lee (KES (1), 2005)

Power-Aware Scalable Pipelined Booth Multiplier. - Hanho Lee (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005)

A high-speed low-complexity Reed-Solomon decoder for optical communications. - Hanho Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2005)

Dynamic Partial Reconfigurable FIR Filter Design. - Yeong-Jae Oh; Hanho Lee; Chong Ho Lee (ARC, 2006)

A high-speed, low-complexity radix-24 FFT processor for MB-OFDM UWB systems. - Jeesung Lee; Hanho Lee; Sang-in Cho; Sangsung Choi (ISCAS, 2006)

A reconfigurable FIR filter design using dynamic partial reconfiguration. - Yeong-Jae Oh; Hanho Lee; Chong Ho Lee (ISCAS, 2006)

Implementation of a FIR Filter on a Partial Reconfigurable Platform. - Hanho Lee; Chang-Seok Choi (KES (3), 2006)

Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applications. - Yong-Min Lee; Chang-Seok Choi; Seung-Gon Hwang; Hyun Dong Kim; Chul Hong Min; Jaehyun Park 003; Hanho Lee; Tae-Seon Kim; Chong Ho Lee (ARC, 2007)

A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders. - Seungbeom Lee; Hanho Lee; Jongyoon Shin; Je-Soo Ko (ISCAS, 2007)

A Partial Self-Reconfigurable Adaptive FIR Filter System. - Chang-Seok Choi; Hanho Lee (SiPS, 2007)

A Self-Reconfigurable Adaptive FIR Filter System on Partial Reconfiguration Platform. - Chang-Seok Choi; Hanho Lee (IEICE Trans. Inf. Syst., 2007)

A Design and Performance of 4-Parallel MB-OFDM UWB Receiver. - Cheol-Ho Shin; Sangsung Choi; Hanho Lee; Jeong-Ki Pack (IEICE Trans. Commun., 2007)

Flexible LDPC decoder architecture for high-throughput applications. - Sangmin Kim; Gerald E. Sobelman; Hanho Lee (APCCAS, 2008)

40-Gb/s two-parallel Reed-Solomon based Forward Error Correction architecture for optical communications. - Seungbeom Lee; Hanho Lee; Chang-Seok Choi; Jongyoon Shin; Je-Soo Ko (APCCAS, 2008)

A high performance four-parallel 128/64-point radix-24 FFT/IFFT processor for MIMO-OFDM systems. - Hang Liu; Hanho Lee (APCCAS, 2008)

Two bit-level pipelined viterbi decoder for high-performance UWB applications. - Yong-Je Goo; Hanho Lee (ISCAS, 2008)

Adaptive quantization in min-sum based irregular LDPC decoder. - Sangmin Kim; Gerald E. Sobelman; Hanho Lee (ISCAS, 2008)

A high-speed four-parallel radix-24 FFT/IFFT processor for UWB applications. - Minhyeok Shin; Hanho Lee (ISCAS, 2008)

A Discrepancy-Computationless RiBM algorithm and its architecture for BCH decoders. - Sangho Yoon; Hanho Lee (SoCC, 2008)

Two-parallel Reed-Solomon based FEC architecture for optical communications. - Seungbeom Lee; Chang-Seok Choi; Hanho Lee (IEICE Electron. Express, 2008)

A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders. - Seungbeom Lee; Hanho Lee (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

A High-Speed Two-Parallel Radix-24 FFT/IFFT Processor for MB-OFDM UWB Systems. - Jeesung Lee; Hanho Lee (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008)

High-speed low-complexity three-parallel reed-solomon decoder for 6-Gbps mmWave WPAN systems. - Chang-Seok Choi; Hanho Lee (ECCTD, 2009)

Two-parallel concatenated BCH super-FEC architecture for 100-GB/S optical communications. - Sangho Yoon; Hanho Lee; Kihoon Lee; Chang-Seok Choi; Jongyoon Shin; Jongho Kim; Je-Soo Ko (SiPS, 2009)

Low-cost variable-length FFT processor for DVB-T/H applications. - Kisun Jung; Hanho Lee (APCCAS, 2010)

High-Speed Two-Parallel Concatenated BCH-Based Super-FEC Architecture for Optical Communications. - Sangho Yoon; Hanho Lee; Kihoon Lee (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010)

A high-throughput LDPC decoder architecture for high-rate WPAN systems. - Kyung-Il Baek; Hanho Lee; Chang-Seok Choi; Sangmin Kim; Gerald E. Sobelman (ISCAS, 2011)

A high-speed low-complexity modified radix-25 FFT processor for gigabit WPAN applications. - Taesang Cho; Hanho Lee; Jounsup Park; Chulgyun Park (ISCAS, 2011)

An area-efficient truncated inversionless Berlekamp-Massey architecture for Reed-Solomon decoders. - Jeong-In Park; Hanho Lee; Seongsoo Lee (ISCAS, 2011)

Low-complexity filter and interpolator design for ATSC DTV systems. - Yong-Kyu Kim; Chang-Seok Choi; Hanho Lee; Jin-Gyun Chung (ISOCC, 2011)

High-Throughput Low-Complexity Four-Parallel Reed-Solomon Decoder Architecture for High-Rate WPAN Systems. - Chang-Seok Choi; Hyo-Jin Ahn; Hanho Lee (IEICE Trans. Commun., 2011)

Low-Complexity Multi-Mode Memory-Based FFT Processor for DVB-T2 Applications. - Kisun Jung; Hanho Lee (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

Low Complexity Filter Architecture for ATSC Terrestrial Broadcasting DTV Systems. - Yong-Kyu Kim; Chang-Seok Choi; Hanho Lee (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011)

A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes. - Sangmin Kim; Gerald E. Sobelman; Hanho Lee (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Biochemical sensor interface circuits with differential difference amplifier. - Shin-Il Lim; In-Sub Choi; Hanho Lee (APCCAS, 2012)

Concatenated non-binary LDPC and HD-FEC codes for 100Gb/s optical transport systems. - Chang-Seok Choi; Hanho Lee; Noriaki Kaneda; Young-Kai Chen (ISCAS, 2012)

A novel method of constructing Quasi-Cyclic RS-LDPC codes for 10GBASE-T Ethernet. - Seong-In Hwang; Hanho Lee; Shin-Il Lim (ISCAS, 2012)

An ultra high-speed time-multiplexing Reed-Solomon-based FEC architecture. - Jeong-In Park; Jewong Yeon; Seung-Jun Yang; Hanho Lee (ISOCC, 2012)

A High-Speed Low-Complexity Time-Multiplexing Reed-Solomon-Based FEC Architecture for Optical Communications. - Jeong-In Park; Hanho Lee (IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012)

Implementations of Signal-Processing Algorithms for OFDM Systems. - Ming-Der Shieh; Yin-Tsung Hwang; Hanho Lee; Chirn Chye Boon; Zhiyuan Yan (J. Electr. Comput. Eng., 2012)

A High-Speed Low-Complexity Concatenated BCH Decoder Architecture for 100 Gb/s Optical Communications. - Kihoon Lee; Han-Gil Kang; Jeong-In Park; Hanho Lee (J. Signal Process. Syst., 2012)

High-performance iterative BCH decoder architecture for 100 Gb/s optical communications. - Jewong Yeon; Hanho Lee (ISCAS, 2013)

A High-Speed Low-Complexity Modified Radix-25 FFT Processor for High Rate WPAN Applications. - Taesang Cho; Hanho Lee (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Block-Circulant RS-LDPC Code: Code Construction and Efficient Decoder Design. - Seong-In Hwang; Hanho Lee (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad standard. - Sabooh Ajaz; Hanho Lee (APCCAS, 2014)

An efficient radix-4 Quasi-cyclic shift network for QC-LDPC decoders. - Sabooh Ajaz; Hanho Lee (IEICE Electron. Express, 2014)

Parallel block-layered nonbinary QC-LDPC decoding on GPU. - Huyen Thi Pham; Sabooh Ajaz; Hanho Lee (SiPS, 2015)

Efficient multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad applications. - Sabooh Ajaz; Hanho Lee (Integr., 2015)

Block-Layered Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes. - Chang-Seok Choi; Hanho Lee (J. Signal Process. Syst., 2015)

Low latency check node unit architecture for nonbinary LDPC decoding. - Huyen Thi Pham; Hanho Lee (APCCAS, 2016)

A delay-efficient ring-LWE cryptography architecture for biometric security. - Tuy Nguyen Tan; Hanho Lee (ISCAS, 2017)

Parallel architecture for concatenated polar-CRC codes. - Seunghun Oh; Hanho Lee (ISOCC, 2017)

High-throughput partial-parallel block-layered decoding architecture for nonbinary LDPC codes. - Huyen Thi Pham; Sabooh Ajaz; Hanho Lee (Integr., 2017)

Two-Extra-Column Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes. - Huyen Thi Pham; Hanho Lee (IEEE Trans. Very Large Scale Integr. Syst., 2017)

Reduced-Complexity Trellis Min-Max Decoder for Non-Binary Ldpc Codes. - Huyen Pham Thi; Hanho Lee (ICASSP, 2018)

High-Secure Low-Latency Ring-LWE Cryptography Scheme for Biomedical Images Storing and Transmitting. - Tuy Nguyen Tan; Hanho Lee (ISCAS, 2018)

Efficient Four-way Row-splitting Layered QC-LDPC Decoder Architecture. - Tram Thi Bao Nguyen; Hanho Lee (ISOCC, 2018)

Basic-Set Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes With High-Order Galois Fields. - Huyen Thi Pham; Hanho Lee (IEEE Trans. Very Large Scale Integr. Syst., 2018)

Simplified Variable Node Unit Architecture for Nonbinary LDPC Decoder. - Huyen Pham Thi; Cuong Dinh The; Xuan Nghia Pham; Hung Dao Tuan; Hanho Lee (APCCAS, 2019)

High-Secure Fingerprint Authentication System Using Ring-LWE Cryptography. - Tuy Nguyen Tan; Hanho Lee (IEEE Access, 2019)

Low-complexity multi-mode multi-way split-row layered LDPC decoder for gigabit wireless communications. - Tram Thi Bao Nguyen; Hanho Lee (Integr., 2019)

Half-row modified two-extra-column trellis min-max decoder architecture for nonbinary LDPC codes. - Huyen Pham Thi; Hanho Lee; Xuan Nghia Pham (Integr., 2019)

Efficient $k$-Parallel Pipelined NTT Architecture for Post Quantum Cryptography. - Phap Duong-Ngoc; Yong-Jin Kim; Hanho Lee (ISOCC, 2020)

Efficient Check Node Unit Architecture for Non-binary Quasi-Cyclic LDPC Codes. - Thang Xuan Pham; Hanho Lee (ISOCC, 2020)

Efficient NewHope Cryptography Based Facial Security System on a GPU. - Phap Duong-Ngoc; Tuy Nguyen Tan; Hanho Lee (IEEE Access, 2020)

High-Efficient Nonbinary LDPC Decoder with Early Layer Decoding Schedule. - Thang Xuan Pham; Hanho Lee (ISCAS, 2021)

Configurable Butterfly Unit Architecture for NTT/INTT in Homomorphic Encryption. - Phap Duong-Ngoc; Tuy Nguyen Tan; Hanho Lee (ISOCC, 2021)

Novel Performance Evaluation Approach of AMBA AXI-Based SoC Design. - Tuy Nguyen Tan; Phap Duong-Ngoc; Thang Xuan Pham; Hanho Lee (ISOCC, 2021)

Minimal-Set Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes. - Thang Xuan Pham; Tuy Nguyen Tan; Hanho Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2021)

Toward A Real-Time Elliptic Curve Cryptography-Based Facial Security System. - Tuy Tan Nguyen; Hanho Lee (APCCAS, 2022)

Flexible GPU-Based Implementation of Number Theoretic Transform for Homomorphic Encryption. - Phap Duong-Ngoc; Thang Xuan Pham; Hanho Lee; Tuy Tan Nguyen (ISOCC, 2022)

Low-Complexity Architecture of Finding First Four Minimum Values for Non-binary LDPC Decoders. - Thang Xuan Pham; Phap Duong-Ngoc; Hanho Lee; Tuy Tan Nguyen (ISOCC, 2022)

Configurable Mixed-Radix Number Theoretic Transform Architecture for Lattice-Based Cryptography. - Phap Duong-Ngoc; Hanho Lee (IEEE Access, 2022)

Low-Complexity Multi-Size Circular-Shift Network for 5G New Radio LDPC Decoders. - Tuy Tan Nguyen; Tram Thi Bao Nguyen; Hanho Lee (Sensors, 2022)

Efficient First Four Minimum Values Finder for NB-LDPC Decoders With Compressed Messages. - Thang Xuan Pham; Hanho Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2022)

CKKS-Based Homomorphic Encryption Architecture using Parallel NTT Multiplier. - Tuy Tan Nguyen; Jisu Kim; Hanho Lee (ISCAS, 2023)

Twiddle Factor Generator Architecture for Number Theoretic Transform. - Chulwoo Lee; Hanyoung Lee; Phap Duong-Ngoc; Hanho Lee (ISOCC, 2023)

Pipelined Key Switching Accelerator Architecture for CKKS-Based Fully Homomorphic Encryption. - Phap Duong-Ngoc; Hanho Lee (Sensors, 2023)

Area-Efficient Number Theoretic Transform Architecture for Homomorphic Encryption. - Phap Duong-Ngoc; Sunmin Kwon; Donghoon Yoo; Hanho Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Hamming-Distance Trellis Min-Max-Based Architecture for Non-Binary LDPC Decoder. - Thang Xuan Pham; Tuy Tan Nguyen; Hanho Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

Configurable Encryption and Decryption Architectures for CKKS-Based Homomorphic Encryption. - Jaehyeok Lee; Phap Duong-Ngoc; Hanho Lee (Sensors, 2023)

Configurable Memory-Based NTT Architecture for Homomorphic Encryption. - Stefanus Kurniawan; Phap Duong-Ngoc; Hanho Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2023)

An Efficient Unified Polynomial Arithmetic Unit for CRYSTALS-Dilithium. - Thang Xuan Pham; Phap Duong-Ngoc; Hanho Lee (IEEE Trans. Circuits Syst. I Regul. Pap., 2023)

Efficient Polynomial Arithmetic and Hash Modules for ML-DSA and ML-KEM Standards. - Quang Dang Truong; Hanho Lee (APCCAS, 2024)

Compact 217 NTT Architecture for Fully Homomorphic Encryption. - Rella Mareta; Hanho Lee (ISCAS, 2024)

Automorphism Architecture for Bootstrapping Homomorphic Encryption. - Hanyoung Lee; Hanho Lee (ISOCC, 2024)

Configurable Arithmetic Core Architecture for RNS-CKKS Homomorphic Encryption. - Chulwoo Lee; Hanyoung Lee; Ardianto Satriawan; Hanho Lee (IEEE Access, 2024)

A Bootstrapping-Capable Configurable NTT Architecture for Fully Homomorphic Encryption. - Rella Mareta; Ardianto Satriawan; Phap Duong-Ngoc; Hanho Lee (IEEE Access, 2024)

Integer Modular Multiplication With Barrett Reduction and Its Variants for Homomorphic Encryption Applications: A Comprehensive Review and an Empirical Study. - Ardianto Satriawan; Rella Mareta; Hanho Lee (IEEE Access, 2024)

Efficient Low-Latency Hardware Architecture for Module-Lattice-Based Digital Signature Standard. - Quang Dang Truong; Phap Duong-Ngoc; Hanho Lee (IEEE Access, 2024)

Hardware Circuits and Systems Design for Post-Quantum Cryptography - A Tutorial Brief. - Jiafeng Xie; Wenfeng Zhao; Hanho Lee; Debapriya Basu Roy; Xinmiao Zhang 001 (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

A Configurable ML-KEM/Kyber Key-Encapsulation Hardware Accelerator Architecture. - Hyunseon Kim; Haesung Jung; Ardianto Satriawan; Hanho Lee (IEEE Trans. Circuits Syst. II Express Briefs, 2024)

Secure and Reliable 6G Communications with BCH-Based GLDPC and Kyber. - Linh Nguyen; Cheol-Hong Min; Hanho Lee; Tuy Tan Nguyen (ICCE, 2025)

Base Conversion RNS using Hybrid Barret-Karatsuba-Based Modulus Prime Cores for Homomorphic Multiplication. - Muhammad Ogin Hasanuddin; Rafael Aditya Cahyo W; Infall Syafalni; Nana Sutisna; Hanho Lee; Trio Adiono (ISCAS, 2025)

An Efficient NTT-Based Polynomial Multiplication Architecture for BFV Homomorphic Encryption. - Rella Mareta; Ardianto Satriawan; Hanho Lee (ISCAS, 2025)

Exploring Possibilities of BFV-based Homomorphic Encryption for Privacy-Preserving Image Processing. - Ardianto Satriawan; Rella Mareta; Hanho Lee (ISCAS, 2025)

Highly-Efficient Hardware Architecture for ML-KEM PQC Standard. - Haesung Jung; Quang Dang Truong; Hanho Lee (IEEE Open J. Circuits Syst., 2025)

Homomorphic Evaluation Cluster Architecture for Fully Homomorphic Encryption. - Hanyoung Lee; Ardianto Satriawan; Hanho Lee (IEEE Open J. Circuits Syst., 2025)

Hybrid Number Theoretic Transform Architecture for Homomorphic Encryption. - Quang Dang Truong; Phap Duong-Ngoc; Hanho Lee (IEEE Trans. Very Large Scale Integr. Syst., 2025)